mhytr
Member level 3
We often see AHB or APB in SOC system using ARM CPU and other bus such WISHBONE is also used in some 32-bit CPU system.
But in my design case,a 8-bit CPU(ex.8051) is enough to read/write the 8-bit control/status registers in the co-processors(maybe 3 or 4).And i want to make the co-processors access the data in the RAM directly,which is to be processed.So i am trying to design a bus to connect the CPU,the processors ,and an arbiter is also needed.But i can hardly find a 8-bit bus design in the papers.So i want to know whether my design is realizable and resonable or not? Thanks!
As an alternative,I can connected all the control/status registers and RAM to the 8-bit CPU and map them as outside RAM.But the CPU will take over all the data transfers,which takes more time compared to using a bus.
But in my design case,a 8-bit CPU(ex.8051) is enough to read/write the 8-bit control/status registers in the co-processors(maybe 3 or 4).And i want to make the co-processors access the data in the RAM directly,which is to be processed.So i am trying to design a bus to connect the CPU,the processors ,and an arbiter is also needed.But i can hardly find a 8-bit bus design in the papers.So i want to know whether my design is realizable and resonable or not? Thanks!
As an alternative,I can connected all the control/status registers and RAM to the 8-bit CPU and map them as outside RAM.But the CPU will take over all the data transfers,which takes more time compared to using a bus.