help regarding inout port in testbench

illegal output or inout port connection

Hi,
i am having a problem with the inout port. how can i declare the inout port in my testbench. i am using Modelsim 6.0 and when i declare my signal as inout, it gives compile time error saying illegal reference to my signal, when i declare it as reg, it compiles ok but when i load my design for simulation, it says " Illegal output or inout port connection " and load failes. help me to solve this problem

thanks
sawaak

illegal output or inout port connection

Hi sawaak,
I could not understand how you are defining ports in a testbench ? Actually the ports are already defined by the DUT. You can only declare reg and wire in a testbench and use it in your testbench. Both reg and wire can be used to either read from or write to a testbench. If this is not clear please reply back with little more details. Also you can post your testbench if any problem is still there.

Best Regards,

illegal output or inout port connection

Hi,
sorry for the misconception, by declaring ports in testbench, i mean the same thing as how to define the datatype for the signals.
we use reg for inputs and wire for outputs in testbench. but what should we use when we have inout port in our module.
lets say i have a module name m.

module m (in,clk,out,data_bus);
input in,clk;
output out;
inout data_bus;
..........
endmodule

then to create testbench, i use

module test;
reg in,CLK;
reg [15:0] DATA_REG;
wire [15:0] DATA_BUS;

wire OUT;


m mym (in,CLK,OUT,DATA_BUS);

initial
CLK = 1'b0;

always
#5 CLK = !CLK;

initial
begin
........
DATA_BUS = 16'hfff0;
........
end

assign DATA_BUS = DATA_REG;

endmodule

this compiles OK and does not give error messeage when i load my design for simulation, but i does not give the result i want , if i declare DATA_BUS as inout, it gives error.
hope i have now tell the problem quite clearly, tell me what to do?

thanks
sawaak

modelsim illegal output or inout port connection

When I run that in Modelsim, it complains about your attempted initialization of DATA_BUS. It's just a wire, so it doesn't make sense to try to initialize its value. Even if it did, you have an assign statement a little further down.

What results are you trying to achieve? Maybe we can help you rewrite your code.

illegal output or inout port connection modelsim

Hi,
sorry for the mistake, this is the result of various combinations i try , actually i have initialized DATA_REG, and i used assign to give that data to DATA_BUS.

what i am trying to achieve is that i have a data_bus in my main module, declared as inout port. now i want to check my main module. for that i have to supply data to the data_bus in my test module. i used inout in testbench but it produces error. i can not use wire, as u mention, it cant hold the value, so i try to declare data_bus as wire to connect to the output of my main module and declare data_reg as reg to hold the value, and used assign to pass the value to the data_bus, this does not produce any error, but i am not getting required functionality. as my supplied data does not appear on the data_bus.
what i need is a solution to test the data_bus of my main module, that is, i supply the data from the test bench and it should appear on the data bus.

thanks
sawaak

inout testbench

I think your testbench needs a separate register to store the value that you want to drive onto the bus.
How about this? The testbech drives two different registers onto the bus at different times.