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physical design jobs- vlsi design

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SDC

When we submit my netlist after DFT to BE Enginer, they want me to provide them SDC file. But I don't know how to produce the file or we should to write it out? And what's the difference between it and top constraint script file? Many thanks!
 

Re: SDC

SDC file is basically the design constraints file. It is used by the physical designer to implement the chip physically. It has to be developed by the logic designer who is the person to know the timing constraints associated with input and output.
 

Re: SDC

Hi
SDC file contains the constraints for Synthesis, Clocking, Timing, Power, Test, Environmental & Operating conditions.It is proven and popular format for describing the design constraints.
Generally BE engineer wants Timing constraints information in SDC format.
You can write the file in the same way as you might have written the tcl file for timing.
 

SDC

SDC-synopsys design constrain
you can generate this file in PT or DC(write_sdc?) when you read you design into DC memory and apply timing contrain.
 

Re: SDC

SDC is the design constraints fie.
It incorpotares all the constraints for the implementation of the chip (synthesis, place-route, scan insertion etc.) This can be treated as a script file haveing all the constraints fed to the synthesis/implementation/pysical tool. The basic constraints for timing etc must be provided by the designer.
if already implemented a chip, all the constraints can be written out in a .sdc file by write_sdc command in sysnopsys DC.
i hope it helpes
 

SDC

write sdc after the completion of STA. this is better. based on this at BE they will write sdf constraints which will guide the place and layout

write them using in PT
 

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