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Some logic in golden design is lost in Verplex clock design

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eddsos

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help: clock in verplex?

When using verplex, i found that some logic in golden design(rtl code) is lost, while revised design is right.
I am confused and do not know what to do.
Since the clock is generated by several input through combination logic, maybe I need setup come attribute on the clock?
Anyone has suggestion?
Thanks.
 

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