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Ask about differential to single-ended amplifier

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peter_hawk

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I want to design a differential to single-ended amplifier.
Input: 0~vdd full swing 500MHz sine wave (vdd=2.7v, 0.5um cmos tech)
The circuit is as following.
My question is the output is not at 50% duty cycle
Can anyone give me some advise.
 

change the invert size such as 0.5/20 and try
and use the full swing opa(two stage)
 

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