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How to reduce the EMI emission??

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nemolee

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Dear All,

I need some advice about reducing EMI emission.
Please give me a hand.
Thanks.

Best Regards.
 

u mean precautions to be taken in layout???

basic steps i know...
1. keep high frequency blocks(like clock gen, synthesizer) in the central portion ->moderate frequency switching blocks in mid-region and low frequency blocks in outer region.

2. high frequency lines shud not hv a sharp bending(antenna effect)

3. circuits lying in btw two parallel high freq lines are exposed to radiation... so take care
 

Also put high speed traces on internal layers between two full coverage ground planes.

Have the ground planes extend to the card edge. Have the power planes pulled back from the board edge by a few layer thicknesses. Stitch the ground planes together with vias around the board edge and every where else you can. Have bypass capacitors between the power and ground plane around the board edges. Put one bypass capacitor on each IC power pin. Use the shortest leads. The opposite side of the board with vias directly to the two planes will work best.
 

in which application?
if in the smps reply for help.
 

following is some advice on reducing EMI:

1) determing critical circuits (90% of problems are caused by less 10% of

circuits);

2) select lowest speed that can meet your system's requirement.

3) use multi-layer board.

4) separate low frequency circuit from high frequency, analog circuits from

digital circuit

5) decouple VCC at every chips VCC and GND pin;

6) pay attention to clock circuits and IO circuits, they are strong emitting souce;

7) test early, test frequently;

nemolee said:
Dear All,

I need some advice about reducing EMI emission.
Please give me a hand.
Thanks.

Best Regards.
Click to expand...
 

Make your design in asynchronous logics, you will have no EMI problem.
 

also try to keep the inductors in such a way they dont couple each others' field

try to keep them perpendicular to each other

and if possible try to cover the circuit by metallic surface
 

I suggest you read a book:printed Circuit Board Design Techniques for EMC Compliance
 

1) EMR is proportional to the current exchange speed.
Therefore when the speed is critical, minimize the signal current.
For example, use lower voltage levels, which provide lower currents.
The sequential resistors sometimes are used to drop the current.
LVDS standard is useful because of low voltage and
that the signal ring provides both small radiation and high noise immunity.
2) If the signal line impedance is not in respect to the source-destination impedance
then such a line is a good antenna for some high frequencies which are derived from this line length and form.
Therefore such lines may be minimized by the length.
Or the proper impedances can be selected to minimize both radiation and signal reflections.
 

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