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How to create a sine wave with verilog ?

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1. use Matlab to gen. a fix-point sin pcm code.
2. in verilog sim test bench. use $readmemh to put the pcm code to a Bus.
3. use waveform viewer to show the Bus data as "Analog".
 
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    kermit

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nand_gates:

Why does is this Verilog cordic-like algorithm stable

assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};

and not the more traditional algorithm where the second line would read

assign cos = cos_r - {sine_r[7], sine_r[7], sine_r[7], sine_r[7:3]}; ?

This last line causes the amplitude to diverge.

Thanks,
mobedwell
 

From Cordic literature, it's obvious that the "more traditional" symmetrical form you're asking for would actually require an additional factor to achieve convergence.
See e.g.: CORDIC - Wikipedia, the free encyclopedia

It's not that obvious in my opinion, why the modification in the present algorithm achieves the required correction. But I assume, that the equivalence can be shown.

Another not obvious property of the fixed point implementation is, that it's apparently stable (with a small superimposed limit cycle) for different divider ratios, not only 8.
 

I finally found an explanation for the correction in the algorithm for generating the sine wave. This is a modified cordic algorithm called the "Goertzel Algorithm". For a good explanation, see paragraph 5 in the accompanying link.

**broken link removed**

Additional information on this algorithm can be found on wikipedia at

Goertzel algorithm - Wikipedia, the free encyclopedia
 

Use a Numerically controlled oscillator. The aforementioned CORDIC too is used, but use NCO. NCO is used in many places.

I only have the vhdl code, no verilog, so not posting it here.
 

ninju,

Please go ahead and post the vhdl code. I am sure I can figure it out.

Thanks.
 

regarding NCO, here's the thread. I myself referred to this while programming.

https://www.edaboard.com/threads/117304/

i haven't got the exact frequency for which i designed. So, if you just want to generate sin and cos, regardless of frequency, i'll post it here.
 

nand_gates,

Can you provide a reference for your algorithm? It seems very stable, but I would like some mathematical verifaction to make me feel comfortable using it.

Thanks,
Mike
 

Re: verilog sine wave

1 Lookup table
2 cordic
 

Re: verilog sine generator

nand_gates said:
Here is the code ur looking for I am posting it here one more time!
Hope this helps!

Code: 
module sine_cos(clk, reset, en, sine, cos);
   input clk, reset, en;
   output [7:0] sine,cos;
   reg [7:0] sine_r, cos_r;
   assign      sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
   assign      cos  = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
   always@(posedge clk or negedge reset)
     begin
         if (!reset) begin
             sine_r <= 0;
             cos_r <= 120;
         end else begin
             if (en) begin
                 sine_r <= sine;
                 cos_r <= cos;
             end
         end
     end
endmodule // sine_cos
Click to expand...



thank you for the code but m not getting the answer ..
for cos = 120 i got sine = 15 and for cos = 30 i got sine = 3 ..
so please clarify your answer..
i am waiting for your reply...
 

Re: verilog sine generator

plz explain that code :( i didnlt understand it
 

The operation principle of the code presented in post #5 has been explained by nand_gates and thoroughly discussed in this thread. If you don't get it, please refer to general CORDIC literature, e.g. https://en.wikipedia.org/wiki/CORDIC.
 

how many stages should be there if i want to design a counter that counts 5-2-0-7-5

i'm confused .
8 stages or 4 stages??
 

Re: verilog sine generator

I want to generate a sine wave with 50Hz and peak amplitude 5.Can you please give the verilog code for that
 

raiyani said:
// sine wave generation

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sine_package.all;

entity sine_wave is
port( clock, reset, enable: in std_logic;
wave_out: out sine_vector_type);
end;

architecture arch1 of sine_wave is
type state_type is ( counting_up, change_down, counting_down, change_up );
signal state, next_state: state_type;
signal table_index: table_index_type;
signal positive_cycle: boolean;
begin

process( clock, reset )
begin
if reset = '1' then
state <= counting_up;
elsif rising_edge( clock ) then
if enable = '1' then
state <= next_state;
end if;
end if;
end process;

process( state, table_index )
begin
next_state <= state;
case state is
when counting_up =>
if table_index = max_table_index then
next_state <= change_down;
end if;
when change_down =>
next_state <= counting_down;
when counting_down =>
if table_index = 0 then
next_state <= change_up;
end if;
when others => -- change_up
next_state <= counting_up;
end case;
end process;

process( clock, reset )
begin
if reset = '1' then
table_index <= 0;
positive_cycle <= true;
elsif rising_edge( clock ) then
if enable = '1' then
case next_state is
when counting_up =>
table_index <= table_index + 1;
when counting_down =>
table_index <= table_index - 1;
when change_up =>
positive_cycle <= not positive_cycle;
when others =>
-- nothing to do
end case;
end if;
end if;
end process;

process( table_index, positive_cycle )
variable table_value: table_value_type;
begin
table_value := get_table_value( table_index );
if positive_cycle then
wave_out <= std_logic_vector(to_signed(table_value,sine_vector_type'length));
else
wave_out <= std_logic_vector(to_signed(-table_value,sine_vector_type'length));
end if;
end process;

end;
Click to expand...

wat about work.sine_package??? without it, this code is not working... please include this package also....asap
 

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