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  1. #1
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    verilog sine wave

    Anyone can tell me how to create a sine wave with verilog ? thanx !

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    verilog sin

    Do you want to make sine wave for the test bench or do you want to make a circuit which generates sine wave?
    For the test bench you can make a look up table. If you want to make a digital circuit then try making a pwm generator.



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    verilog sine

    Quote Originally Posted by feel_on_on
    Anyone can tell me how to create a sine wave with verilog ? thanx !
    Not possible.. You can use CORDIC algorithm if u just want the sine/cosine values corresponding to an angle..


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    sine wave verilog

    If you use sine wave to do simulation, you can use pli to achieve it


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    verilog sine generator

    Here is the code ur looking for I am posting it here one more time!
    Hope this helps!

    Code:
    module sine_cos(clk, reset, en, sine, cos);
       input clk, reset, en;
       output [7:0] sine,cos;
       reg [7:0] sine_r, cos_r;
       assign      sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
       assign      cos  = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
       always@(posedge clk or negedge reset)
         begin
             if (!reset) begin
                 sine_r <= 0;
                 cos_r <= 120;
             end else begin
                 if (en) begin
                     sine_r <= sine;
                     cos_r <= cos;
                 end
             end
         end
    endmodule // sine_cos


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  6. #6
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    verilog sin cos

    Verilog-A maybe solve your problem.



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    sine function in verilog

    Hi, nand_gates

    Could you paste your waveform? I don't think that it can bring the sine wave.

    Thanks



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    sine wave in verilog

    Hi,nand_gates
    what simulation tools should be used to create sine
    wave with ur code?



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    verilog sine cos

    If you want to generate sin stimulus in a testbench, you can create sin wave in other tools such as matlab or SPW then write out the data to a file ,finally reading the file in testbench written in verilog.



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    sine wave using verilog

    Any simulation tool will do!
    The trick here is the generated sine output is in two's complement
    integer format or its signed integer. To conver it into unsigned you
    will have to invert the msb.
    If you are using modelsim wave form viewer you can change the format
    of wave to signed integer analog you will see sine wave....



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    sine in verilog

    you can create a sine wave with DDS technology,

    for detail, please visit <www.analog.com> and search DDS.





    Quote Originally Posted by feel_on_on
    Anyone can tell me how to create a sine wave with verilog ? thanx !



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    generating sine wave in vhdl

    nand_gates! please tell me the code theory?i never had understanded it!



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    verilog generate sine wave

    Another way: using the Taylor expansion coefficients of sin and cosine, for DDS which is basically same idea as using matlab, you need more tools and hence extra complexity.

    Question: Can we use Verilog-AMS for this sort of tasks? or even System-C?



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    verilog sine wave generator

    Here is my result for easy implement sinewave, including control

    [1] Frequency (phase Step)
    [2] Phase offset



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    Re: How to create a sine wave with verilog ?

    you try to make a look up table considering the values for a sine wave and store it in its internal RAM.. i hope u got..



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    Re: How to create a sine wave with verilog ?

    I found the nice code by nand_gates here. So thank you!
    The code works fine, but unfortunately I'm too stupid to discover what is happening inside it.
    Can anyone explain this code in more details? Please!!!
    What is the main idea in the algorithm?
    What if I want to change the bit width for example?

    Warmly thanks for any explanation!



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    Re: How to create a sine wave with verilog ?

    Whats is being done in the code is 'signed magnitude extension'. This is done by appending digits to the most significant side of the number.

    If you want to increase the width then you should be extending the MSB instead of 7 (which is the MSB in this case).



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    Re: How to create a sine wave with verilog ?

    can you use lookup table to create?



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    Re: How to create a sine wave with verilog ?

    It's a second order difference equation acting as an oscillator with zero dampening.
    Code:
    sin(n) = sin(n-1) + a*cos(n-1)
    cos(n) = cos(n-1) - a*sin(n-1)
    In the present case, a is 1/8. It can be basically changed to higher magnitude resolution and lower frequency (=higher phase resolution), but depending on truncation effects, it possibly won't give an exactly periodic output for all a values. I fear, you get a decaying oscillation for some a codings. A correction term (of course disturbing the ingenious simple original design look) could help. Just try.

    As the design is effectively rotating a complex vector, it's also related to CORDIC.



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    Re: How to create a sine wave with verilog ?

    // sine wave generation

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.sine_package.all;

    entity sine_wave is
    port( clock, reset, enable: in std_logic;
    wave_out: out sine_vector_type);
    end;

    architecture arch1 of sine_wave is
    type state_type is ( counting_up, change_down, counting_down, change_up );
    signal state, next_state: state_type;
    signal table_index: table_index_type;
    signal positive_cycle: boolean;
    begin

    process( clock, reset )
    begin
    if reset = '1' then
    state <= counting_up;
    elsif rising_edge( clock ) then
    if enable = '1' then
    state <= next_state;
    end if;
    end if;
    end process;

    process( state, table_index )
    begin
    next_state <= state;
    case state is
    when counting_up =>
    if table_index = max_table_index then
    next_state <= change_down;
    end if;
    when change_down =>
    next_state <= counting_down;
    when counting_down =>
    if table_index = 0 then
    next_state <= change_up;
    end if;
    when others => -- change_up
    next_state <= counting_up;
    end case;
    end process;

    process( clock, reset )
    begin
    if reset = '1' then
    table_index <= 0;
    positive_cycle <= true;
    elsif rising_edge( clock ) then
    if enable = '1' then
    case next_state is
    when counting_up =>
    table_index <= table_index + 1;
    when counting_down =>
    table_index <= table_index - 1;
    when change_up =>
    positive_cycle <= not positive_cycle;
    when others =>
    -- nothing to do
    end case;
    end if;
    end if;
    end process;

    process( table_index, positive_cycle )
    variable table_value: table_value_type;
    begin
    table_value := get_table_value( table_index );
    if positive_cycle then
    wave_out <= std_logic_vector(to_signed(table_value,sine_vector _type'length));
    else
    wave_out <= std_logic_vector(to_signed(-table_value,sine_vector_type'length));
    end if;
    end process;

    end;



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