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1. Crosstalk: Coupling capacitance between adjacent wires, wherein transitions in one wire may cause or inhibit transitions in another wire thereby leading to either noise, glitches or delayed transitions
2. IR-drop: Poor VDD or ground levels in certains subckts of layout causing increased delays in the paths that lie in such subckts.
3. Electromigration: Constant flow of DC current through a wire, can cause wire degradation through voids formed by electron winds and depositions.
4. L di/dt noise: A relatively newer issue where current flow through a wire loops through to the return path which is either VDD or ground, causing current loops reading to an inductive coil similar to a transformer, causing magnetic fields
2, 3 may not be pure signal-integrity issues, but are nevertheless CAD based issues that arise from poor CAD design.
Substrate coupling is the coupling between ground and the cells. The delay offered by
the cells decreases with finer geometries as the cells are getting narrower and the substrate coupling is decreasing between the ground(substrate) is decreasing.
On the other hand nets are are coming closer to each other and thus the coupling between the nets increases and delay offered by the interconnects increases.
Thats is the reason why interconnect delays dominate in 90 nm and below compared to cell delays
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