Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Input rise time of start/stop pulse to the TDC

Status
Not open for further replies.
V

vinogunasekaran

Junior Member level 2
Joined
Sep 19, 2012
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
India
Activity points
1,456
How much should be the input rise time of the start/stop pulse to a TDC? What determines it?
 

Hi,

I don't understand your question .... because we don't know which IC you use nor do we know your application requirements.

General answer:
If I wanted to know this, I'd read it's datasheet.

Klaus
 

At least fast enough to allow clear edge detection, preferably fast enough not to introduce additional timing uncertainty.
 

KlausST said:
Hi,

I don't understand your question .... because we don't know which IC you use nor do we know your application requirements.

General answer:
If I wanted to know this, I'd read it's datasheet.

Klaus
Click to expand...
ya, for IC's i can see the datasheets. But I wanted to design a TDC of my own, say a simple vernier delay line TDC. Based on what should I fix the limit of my input rise time
--- Updated ---

FvM said:
At least fast enough to allow clear edge detection, preferably fast enough not to introduce additional timing uncertainty.
Click to expand...
yes, how much should it be fast, timing uncertainity i get it.
 

Rise time converts noise and logic threshold variations into timing inaccuracy. You can use slower rise time for trigger signals but will face reduced timing accuracy.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top