Measurements of SNR and SFDR of ADC for different input frequencies

Dear all,
I am trying to measure the SNR and SFDR of the output signal from an ADC for an input fs/40, fs/10, fs/5 (fs is the sampling frequency of the ADC). While there is hardly any degradation in SFDR, there is 8dB degradation in SNR when the input frequency is changed from fs/40 to fs/10 and another 8dB degradation in SNR when the input frequency is changed from fs/10 to fs/5. How is the SNR degrading so much while there is hardly any change in SFDR? Is there any relationship between SNR and SFDR? Is this a normal behavior of an ADC or Am I going wrong somewhere?

TIA

By sampling with frequency which is a multiply of signal frequency you are asking yourself for interesting results.

Of course, your circuit might works poorly with higher frequency as well.

Hi,

SNR means signal to noise.

Which value does change? "Signal" or "Noise"?

****
For a more detailed answer we need more detailed informations first:
How do you measure and calculate SNR?
What is your signal source?
What is your sampling frequency source?

Maybe more informations...


Klaus

Dominik is right. With sampling frequency being some integer multiple of the input frequency the quantization noise is not really quite "white", that is randoized and this can have it effect in the SNR you see.

How are you measuring this ? What is your set up ?

Thank you all for the reply. First of all, my input frequency is not exactly fs/10 or fs/5 but close to these values. The frequency of the input signal is taken such that it covers all the codes.
My input frequency is 111*fs/N where N is the number of FFT points.
For calculating the SNR, first I take the fft of the output signal from the ADC, then process it in matlab to get the SNR.

Sorry is this a circuit simulation (what tool are you using) or an actual measurement in the lab ?

If circuit simulation, you are probably not taking the FFT at the right sample point. Are you applying 111*fs/N at all input frequencies ? That might not be correct. You have to do the coherent sampling at each frequency input and input a different input frequency fo each different input.

If you are using Cadence DFII/Spectre, then you have to set the strobe period and strobe delay to sample the signal at the right waveform point if doing a transient. Since you seem to be using the same input frequency, that might be why you are getting a wrong result. If you have Cadence IC6.1x there is a spectrum assistant that plots the DFT automatically

111*fs/N is right and from what I understood this is just an example for one of the input frequencies and this way of choosing the input frequency prevents spectrum leakage. I assume that since Chinmaye
knows how to set up input frequency he knows how to strobe in Cadence and take fft.

I am using cadence to do the simulations. There is no lab setup. Could you please elaborate on this? What is the correct method to calculate SNR

Well, what Cadence dfII/Spectre version are you using ?

If you are using IC6.1.5 then you need to do MATLAB post processing of the output and plot the SNR, SNDR using MATLAB code on the outputs from the simulation - as I am sure you know. Use a different coherent sampling frequency for each input frequency that you want. You you can also use the calculator functions.

If you are using IC6.1.6 and above then there is a built in Spectrum Assistant that automatically plots ENOB, SNDR, SNR and other metrics. If you are using IC6.1.6 and above, use pull down menu->Measurements -> Spectrum. This opens an assistant, Spectrum Assistant.

You have to use strobe delay and strobe period in a transient simulation to sample the waveform for the FFT at a point where the output has settled and therefore the sample is correct for calculating the FFT. For example, if you are doing an FFT on a DAC, you pick a sampling point between the clock sampling points of the DAC when the output is settled in order to get the correct FFT and not the points where the clock is sampling the DAC, since the output is not settled yet.

This paper from Analog Devices might be helpful for your theoretical understanding of the different metrics for ADCs.

https://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

Since I am not sure of your set up in the simulation, I can only guess you might be setting up the FFT or DFT incorrectly. I also don't know how you are calculating SNDR and SNR - so I am just making assumptions.

From the above white paper from Analog Devices (note SINAD is the same as SNDR):

"Signal-to-noise ratio (SNR, or sometimes called SNR-without-harmonics) is calculated from the
FFT data the same as SINAD, except that the signal harmonics are excluded from the
calculation, leaving only the noise terms. In practice, it is only necessary to exclude the first 5
harmonics, since they dominate. The SNR plot will degrade at high input frequencies, but
generally not as rapidly as SINAD because of the exclusion of the harmonic terms."

sutapanaki said:

111*fs/N is right and from what I understood this is just an example for one of the input frequencies and this way of choosing the input frequency prevents spectrum leakage. I assume that since Chinmaye
knows how to set up input frequency he knows how to strobe in Cadence and take fft.

Click to expand...

Dear Sir,
Could you please explain how to calculate SNR in Cadence. I did not understand what you meant by "strobe in cadence and take fft". I am using IC617 version. I just want to make sure that i am not missing out on anything or making a mistake in calculation. Thank you.

Also, I am using a few verilog A blocks in the circuit. Would that affect the calculation of SNR?

Since you are simulating an ADC you have to take its digital output and put it through an ideal DAC to convert to analog. Set up the strobe period in the options of the transient analysis in cadence as Puppet123 explained above. The strope period should be equal to the inverse of your sampling frequency or integer multiple of the sampling frequency. Make sure you sample when the DAC output has settled.Then use one of the spectrum tools in cadens to calculate the SNR. This was explained above again by Puppet123. Or you can import your simulation results to Matlab and do the post-processing there. Your input frequency should be set as you already did Fin=Fs*cycles/N.

Yes, using Verilog-A blocks can affect the SNR because they are ideal blocks and depending on how they are coded they can cause nonindeal behaviours.

What are you using the Verilog-A blocks for - and what type of ADC is it ?

Puppet123 said:

Yes, using Verilog-A blocks can affect the SNR because they are ideal blocks and depending on how they are coded they can cause nonindeal behaviours.

What are you using the Verilog-A blocks for - and what type of ADC is it ?

Click to expand...

I am trying to simulate a pipeline ADC and I am using one verilog A block for switching purpose and this can be replaced by switches. Thank you for the reply. I have another question. For how many cycles should I simulate the ADC before I find the SNR? Suppose I would like to find the SNR at 873KHz and my sampling frequency is 4MSPS, then I am running the simulation for 111 cycles. (Fin*N/Fs = 111 cycles). Am I correct?

It really depends also on the FFT points N. You are using 512. If you used 1024, then you would need 2x more cycles for the same input frequency. The important thing is that cycles and N are mutually prime numbers. And of course, you will have to have some time in the beginning of the simulation to let everything settle to steady state. This initial wait time you better express also in terms of the strobe period that you've set up. This way you are sure that when you really start collecting points for your spectrum measurement you start on a strobe point and not in between strobe point.

Have fs = sampling rate.
Have number of samples or number of FFT bins = Nfft

Say fs=100Mhz.
Say Nfft = 2^6=64.
Say fin = 10MHz.

Need coherent sampling for FFT.

1) Calculate fin/fs x Nfft = 10/100 * 2^6=6.4
2) Find the closest prime number to fin/fs * Nfft or 7
3) New input frequency is then 7/Nfft * fs = 10.9375MHz
4) Input bin is fbin = 7
5) Say circuits settles after 100 ns and we need 64 samples in total for FFT
Then, stop time for transient simulation is set to be 200ns+64*10ns = 740ns.

Dear all,
I would like to thank everyone for your reply. I am able to use the function Spectrummeas in cadence calculator and calculate the SNR of the ADC from that. My SNR improved once i replaced the Verilog-A blocks in the design. Thanks for your help.