Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

micron ddr sysverilog model | Read rand addr | how to get 0s ( not Xs ) ?

Status
Not open for further replies.

ranke

Newbie level 1
Joined
Jun 1, 2020
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Hi,
We run micron ddr4 systemverilog model, it returns 'X' when read from a new address, it returns 'X' while we sould prefer to get '0'.


Thanks,
Ran.
 

Hi,

most probably the contents of the RAM are not defined after pwer up.
--> if you want to read "0" you first have to write "0".


Klaus
 

You must verify certain things with the RAM model first.
There should be a signal called calibration_complete. Please check if that is asserted HIGH at some point as simulation proceeds. Only after that you can W/R from the RAM. Next you need to make sure 0s exist at the address from which you prefer to read.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top