Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Noise simulation of OPAmp

Status
Not open for further replies.

deep_sea

Advanced Member level 4
Joined
Oct 23, 2019
Messages
100
Helped
14
Reputation
28
Reaction score
17
Trophy points
18
Activity points
851
Hi Guys,
I am simulating the noise performance of an opamp. I would like to check if my setup is correct.
The opamp is a two stage miller compensated opamp. The input is a DC + AC small signal.
The WP1 variable is the number of PMOS input transistors and is related to the length of input transistor. For example WP1=48, means W1=48um, L1=1u, WP=480 means W1=480um and L1=10um
According to the following expression: e2n =B/(f*W1*L1), it is expected that input referred noise would be 100 smaller when W1 and L1 are increased 10 times each. In simulation you can see in attachment it has almost no effect.
Could you please check if the simulation setup for noise is correct? does anyone has an explanation?
 

Attachments

  • opamp1.png
    opamp1.png
    22.5 KB · Views: 79
  • noise_analysis.png
    noise_analysis.png
    76 KB · Views: 70
  • input_referred.png
    input_referred.png
    34.1 KB · Views: 68

Do you have a closed loop around this amplifier?
 

If you print the noise sources at 100 Hz, is the input transistor dominating?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top