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[SOLVED] Opinions about SEPIC versus Zeta converters

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d123

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Hi,

I would like anyone interested in these topologies and/or with practical experience or knowledge of both SEPIC and Zeta to share their opinions.

I read that SEPIC positives are that it is more efficient, has lower input ripple; negatives are two RHPZ, high output ripple. Zeta positives are no RHPZ (easier control loop compensation and higher bandwidth possible as a result), low output ripple; negatives are higher input ripple, not as efficient.

Besides choices like needing minimum input ripple or minimum output ripple, say a delicate load would be better with a Zeta, are these topologies to all intents and purposes much of a muchness and amount to the same thing?

When would you choose one or the other and why?

What are real-world experiences and personal design tips and opinions of both?

Separately, as I'm not 100% clear on this one outside of simulation-land (...works wonderfully in the cartoon...) and typical preparatory calculations, please:
Is there anything unrealistic about a SEPIC with a load range of 10mA to 1.3A?
For such a load range, what is minimum inductor ripple I can get away with? Formula I use suggests 40%, is less possible, say 10% or 20% or will inductor saturate and maybe even 40% isn't enough?

Thanks.
 

Many moons ago, I also was curious about the SEPIC topology, but did not have a project to apply it.

Then an opportunity came to build a remote temp/humidity/sunlight data acquisition with a RTC. It had an USB port where with a laptop one could download one month’s worth of data, itself stored in EEPROM.

Long story short the power supply consisted of a solar cell which would power it during bright sunlight plus 4 AA Alkaline cells for heavy overcast or nights. Data required to be acquired at 10 minute intervals 24/7.

Because of the wide voltage range, 8 volts with bright sunlight and below 4 at night with depleted batteries, to power the 5 volt electronics I realized that a SEPIC would be ideal.

Long story short: this converter is difficult to stabilize. I ended up employing a hysteretic controller and operating it in discontinuous mode. Non coupled inductors.

Worked like a champ for almost 10 years before it was damaged by a tractor plowing the field.

That’s my personal experience. I would love to work with the Zeta this time around.
 
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Hi,

Thanks for the feedback. Love to know about your experiences regarding its being hard to stabilize. In these months of simulating three different SEPICS with load steps of 10mA to 1.3A and different loads and Vin min to Vin max, etc., they all supposedly function well with a type 3 compensation that is not far from fSW (100kHz) and 94uF Cout, fb taken at load point - this seems dubious to me as all literature says feedback loop of 1/3rd to 1/10th fSW and RHPZ and second-stage filter reduce/limit bandwidth...

'Worked like a champ for almost 10 years', brilliant! Built to last is good. I like SEPIC, it looks robust and tolerant of component variations and quite 'self-starting'.

Shame there isn't a hybrid SEPIC input and Zeta output (no current ripple either end and very low Vout ripple) design afaik.

I wanted to do something mindless this afternoon so out of curiosity (only to see how truly similar/dissimilar they are) used a SEPIC model that works and swapped component positions to make it a Zeta and only calculated L1 and L2 values and it was an epic fail :laugh: Conclusion - they are entirely different animals. I want to use Zeta more often, it has a real place I feel where SEPIC isn't a perfect fit.

I am under the impression Zeta is bad with battery-powered devices due to current pulse input. I intend to use a SEPIC with a PV panel and another with a battery.

Do you feel that SEPIC lends itself well to PV input given PV Zin must vary all day long? It is used for so many PV circuits as the SMPS...
 

Fortunately for the project, I had the AA cells which were O'rd with the PV cell via diodes. If the PV cell dropped its voltage below those of the AAs, the latter would carry over the load. So I can't really answer whether the SEPIC would be the best option to a PV's constantly changing MPP. The project didn't attempt to track it.

The PV cell was not there as the primary DC source, it was only to reduce the total mAhr draw from the AAs.

Although the project itself lasted almost 10 years, during the first couple of years we had several failures caused by the environmental conditions. Not only humidity and agricultural chemicals would get inside and cause corrosion, but insects sometimes decided that the project was a cozy place to build their colony. It took us two or three designs to get the environmental protection just right.

But the SEPIC circuit remained unchanged throughout.
 
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We have built Sepics to 350kHz, choose Sepic when you want low input ripple ( and can have a quality o/p cap )

Zeta ( or inverse Sepic ) when you need a low o/p cap, and can handle the input ripple on the i/p cap

the faster you make the power stage, the smaller you can make the L's and C's, and the faster you can make the control loop ---

even a humble TLC55 can run a Sepic well at 300kHz ...

of course the Zeta requires high side drive for the mosfet - which is a complication ....

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in the Sepic there is a nice turn off path for the current to the o/p - limiting turn off volt spikes for good layout ...
 
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Thanks for the feedback. Love to know about your experiences regarding its being hard to stabilize. In these months of simulating three different SEPICS with load steps of 10mA to 1.3A and different loads and Vin min to Vin max, etc., they all supposedly function well with a type 3 compensation that is not far from fSW (100kHz) and 94uF Cout, fb taken at load point - this seems dubious to me as all literature says feedback loop of 1/3rd to 1/10th fSW and RHPZ and second-stage filter reduce/limit bandwidth...
IIRC, all the coupled-capacitor topologies (zeta, sepic, cuk...) have multiple RHP zeros. The sepic has two (maybe three?). So the control loop will need to be somewhat slow, if you're operating in CCM. Usually some damping is applied to the coupling capacitor to mitigate this.

Shame there isn't a hybrid SEPIC input and Zeta output (no current ripple either end and very low Vout ripple) design afaik.
Cuk converter. Can be isolated if you want a positive output voltage. Even nastier transfer function though (four RHPZ if I recall correctly).

Honestly, I feel like too much emphasis is placed on the input/output ripple of different topologies for low power designs anyways (like <1hp). If your switching frequency is high and your layout is good, your photocell/battery isn't going to see much pulsating current from a discontinuous input/output current.
 
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Hi,

The damping on Cc is something I've never heard of, thanks.

Really good to know that input and output pulsed current is not so bad. Had visions of cell/battery heating up and exploding.

Asked partly as a crummy discrete-part voltage regulator model I use to fill a simulation gap works fine on a variable DC input or e.g. a 6V + 1V pk-2-pk sine input but it won't simulate with the SEPIC models that simulate well from 0 to 85°C (except for - 15C for no idea why as all parts are - 40C to - 55C capable so I assume Spice models include that ability). Iout of SEPIC into an Rload is smooth with a little ripple for 10mA to 1.3A load, but when I connect 'LDO' with dummy resistor load of 1.5k before it, Iout of SEPIC becomes pulsed current of ~2A - don't understand that.

Besides RHPZs (I pretend they aren't real and the problem disappears - joke), Zeta is more parts, as easy peasy said, high side drive/floating gate drive I read...

Unfortunately, TLC555 model is horrible beyond 50kHz (gets spiky and Vout falls sooner than would expect) and I'd use LMC555 in reality which has no model.

Appreciate input as want to get better understanding of realities of buck- and boost-based converters beyond reading, calculations and simulations to gauge validity of theoretical circuits needed.

Want to add embarrassing kindergarden question (still learning/trying to genuinely understand what's happening during switch tON and tOFF in various converter topologies) with schematic that is related to the main topic: Why is there no SEPIC that replaces L2 with a diode, if it works the same? Higher overall PD of diode compared to inductor? Stability? In my simulations, replacing L2 with a Schottky makes start-up smoother with no initial ringing and steady-state switching much neater/more uniform in magnitude. I assume the L2 version ringing for a few hundred us with three not worrying ripples is non-ideal compensation, is it, or damping missing somewhere? Both versions work the same regarding different Vin and load values. What are reasons not to replace L2 with a diode? Also, can anyone guess without doing maths if my EA compensation scheme is BS and only valid in simulations but likely to be a waste of components in reality? fSW is 100 kHz and I put - talking very approximately - both zeroes around 10 kHz and both poles around 100 kHz or more in the written calculations, but phase/gain plot showed poles fell short by a long way, if I remember correctly.

SEPIC no L2 V1 CLEAN SCHEMATIC.JPG
 

your ckt is missing a choke - has diode instead ...?
 
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Although you are correct that the current's direction in a diode which "would replace" L2 is similar, the reality is that an inductor stores energy in the form of current, whereas a diode only steers the current without storing any energy.
 
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Hi,

your ckt is missing a choke - has diode instead ...?

Good, isn't it? :lol: It's a ZEPIC converter :laugh:

Last lengthy paragraph of previous post explains. Proper circuit has L1 and L2 but that schematic has several 'post-it note' style observations so rather not post it, it's a normal/proper SEPIC anyway... Was 'messing around' today thinking of Cuk but not inverting and it led to that (diode instead of second inductor). Just wanted to know reasons for or against using that modification if output is same as with inductor.

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Hi,

Although you are correct that the current's direction in a diode which "would replace" L2 is similar, the reality is that an inductor stores energy in the form of current, whereas a diode only steers the current without storing any energy.

Great, thanks. So that circuit/version could possibly run into trouble regarding not enough power to drive output at some point? Although it depends on other aspects too, it might handle an amp or so but would probably droop as Iout is raised? I imagine PD in inductor is lower as it is Pcore and Pwire and DCR is always very small (compared to diode Vf x Iout)?
 

another newbie oversight - when the fet turns on there is an enormous current pulse as it shorts out the blocking cap via the diode that shouldn't be there ... and discharges it to zero every time, without contributing anything to the o/p - but rather to watts and stress in the mosfet ....
 
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Hi,

another newbie oversight - when the fet turns on there is an enormous current pulse as it shorts out the blocking cap via the diode that shouldn't be there ... and discharges it to zero every time, without contributing anything to the o/p - but rather to watts and stress in the mosfet ....

Great, thanks, really important. I had a voltmeter on that node, no ammeter, so didn't see that.
 

Hi Akanimo,

Not sure what you mean by switching and averaging. Component values are all in schematic, awol L2 is also 100uH. It was just messing around, as two people have pointed out contras to doing that with a SEPIC, I'll leave that experiment there but curious as to what you think could be done with it.
 

Hi Akanimo,

Not sure what you mean by switching and averaging. Component values are all in schematic, awol L2 is also 100uH. It was just messing around, as two people have pointed out contras to doing that with a SEPIC, I'll leave that experiment there but curious as to what you think could be done with it.

Well, switching models will allow you run transient analysis. Averaging models will allow you run transient analysis (although you will lose the detail, like switching ripples) in addition to DC sweep, small-signal ac analysis, and more. You can also see the frequency response bode plot. Depending on how accurate the model is, it suffices when used for loop compensation. They are a very helpful tool to have especially when one does not have an FRA. Even with an FRA, it's provides a quick means to get such insight.

...L2 is also 100uH
Okay, I'll plot the frequency response of you converter and see what there is. How about the input voltage range and auxiliary voltage value?
 
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Hi,

Thanks, that's very kind of you. I use the TI Tina free version schematic capture and simulation tool and it seems pretty good, it does all the things you mentioned in your last post.

I grabbed an hour today to add roughly guesstimated from datasheets ESR to Cin, CC and Cout caps today, still works as a simulation.

I wouldn't bother doing anything if I were you, unless you really want to, reason why is that I have a long way to go with stuff related to the SEPICs I'm working on, e.g. (horror of the LC) output filter to smooth pulsed current, including linear inrush current limiting stage that doesn't ruin functionality and adding a Voltage feed-forward section, besides incorporating actual triangle wave circuit instead of voltage source. I am doing these circuits a bit slowly by necessity of circumstance and as I want to get to know and understand certain things as well as I personally can hope to.

As you asked, 'though, this one is not the PV panel source one that is 3V to 12 Vin. This one is the 3.7V, 10Ah, 37mOhm internal resistance Li-ion cell source version, Vin = 3V to 3.7V (really 3.2V to 3.7V but allowing lower margin just in case ever needed), Vout = 5.6V and 10mA to 1.3A, fSW = 100 kHz.I want to keep compensation as is but know I have to recalculate values for a much lower crossover...

What is an FRA, please?
 

FRA is probably a frequency response analyser

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Eg you can get the ones by ray ridley engineering.....cost about 12k

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Your sepic power level is very low........you can do a well coupled sepic converter with coupled L's...this essentially works just like a 1:1 flyback.....except you dont need the rcd clamp of a flyback....because when the fet turns off, their is a path through the coupling cap of the sepic to the output.

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With wide vin range, you can use constant off time control to manage the wide range of duty cycles./
COT also means no sub harm oscillation.

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Coilcraft do some well coupled inductors for coupled sepic.

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With a coupled sepic, you must make sure that the LC resonant frequency of the leakage L and the coupling C, is lower than the switching frequency….otherwise you get a lot of LC ringing which heats up the coupled inductor ferrite.
The feedback loop dynamics also get easier with the well coupled sepic....in fact, the dynamics get like the 1:1 flyback ...with the same L's

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The good thing about the sepic, as you know, is that vout can be above or below vin……..this is why it needs the coupling capacitor….as this cap blocks a dc path to the output (like exists in the boost converter)….but when you put the coupling cap there in a boost converter…..you then find you need the second inductor there so that this second inductor can push current the opposite way in the coupling capacitor to make up for the current that went through the capacitor when the fet was off…..so thus the sepic needs its two inductors.
Since basically…the sepic has a voltage of vin across the sepic capacitor….in fact , that is one of the design criteria for any sepic…ie that the voltage ripple on the sepic capacitor should be no more than 10%, and preferably 5%.

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One way of looking at the sepic….as that it’s a variation on the boost converter, but with the blocking cap there so that when vin > vout, there is no dc current rushing into the output…….and its almost as if you are taking the input voltage ……and putting it on the coupling capacitor…because the voltage on the coupling cap is vin for a sepic
When the sepic fet is on….the coupling cap voltage (which equals vin) is across the 2nd inductor…..kind of just like in a boost converter when the boost fet is on, the input voltage is across the boost inductor….so you see the synergies.

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So there is a rule for any capacitor in an smps in steady state…that over a switching cycle, the charge flowing into any capacitor must equal the charge flowing out of the capacitor (otherwise the cap would get charged up to infinite volts and i am certain you are cognisant of this) …….so this is why you need your two inductors in the sepic…because without the 2nd inductor there, you wouldn’t get any current flowing into the coupling cap during the fet on time.

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To ease the dynamics of the uncoupled sepic, you can of course do it in DCM….though admittedly its more challengeing to get dcm over a wide vin range

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When you are doing a sepic at the output of a solar panel…it is in fact easier. This is because for a sepic at the solar output…you will tend to regulate the input current and input voltage of the sepic ….ie , you have an error amplifier to draw current from your solar panel (by the sepic) at nominal maximum current….and when this makes your vin go too low, then the vin regulating error amplifier kicks in to the sepic , and it reduces the input current of the sepic to that level which keeps the vin at the level necessary for MPPT.
…and since you are regulating the input voltage or current of the sepic…so its dynamics are far easier than when you are regulating the output of the sepic

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With the uncoupled sepic in CCM, there is of course the resonant frequency of the two inductors and the coupling cap. This frequency must be less than the crossover frequency of the sepic.
Also, the coupling cap must be big enough in farads such that its v(ripple) is less than 10%...preferably less then 5%.
Basically, with the uncoupled sepic in ccm, there should be an RC damping circuit across the coupling cap….the sizing of the R of this RC is that it should be equal to SQRT(2L/C). The C of this RC should be of the same faradic value as the coupling cap itself.
 
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Hi,

Thanks. Some very interesting information in your post, treez, much appreciated.
 

No probs, ..and i assume you are looking into sepic instead of boost for the 3.7vin to 5.6vout spec because of interest in sepic, and also perhaps you dislike the initial inrush into the boost output cap.
 
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Hi,

I'm focussing on SEPIC as it fitted requirements and to be capricious, I like its handy functionality (Vout = <>Vin) which is useful for PV cells and batteries (e.g. 3V to 3.7Vin for 3.2Vout or 3V to 12Vin and ~5.6Vout). Also, from a limited foray into Zeta converters, SEPIC is really keen to work but Zeta is a nuisance to get to reach Vout and Iout due to high-side switch gate drive requirements, I guess, and needs far more capacitance. All my simulations 'enjoy' astronomical inrush currents that blow the fuse model and seem to match reality of calculated I inrush = Cload x (Vout/tON), so am fitting/trying to fit a linear ICL to inputs.

SEPIC just seems a practical choice besides pulsating output current, is good with VMC, and supposedly can be shut down if there is no load.
 

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