+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Junior Member level 1
    Points: 222, Level: 2

    Join Date
    Oct 2019
    Posts
    19
    Helped
    5 / 5
    Points
    222
    Level
    2

    Verilog and VHDL noise modelling

    Hello guys,
    How can I model the noise using Verilog or VHDL?
    Are there any examples for the following noise modelling:
    White noise
    Thermal noise
    1/f noise
    oscillator noise

    •   AltAdvertisement

        
       

  2. #2
    Super Moderator
    Points: 266,464, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    46,575
    Helped
    14170 / 14170
    Points
    266,464
    Level
    100

    Re: Verilog and VHDL noise modelling

    Your question isn't very specific, what do you want to achieve?

    VHDL and Verilog are digital simulators without means to represent analog signals or sources.

    I can imagine a discrete noise generator as part of a digital signal processing test bench, it could e.g. use the pseudo random function UNIFORM() in IEEE.MATH_REAL and possibly digital filters for spectral shaping.



    •   AltAdvertisement

        
       

  3. #3
    Junior Member level 1
    Points: 222, Level: 2

    Join Date
    Oct 2019
    Posts
    19
    Helped
    5 / 5
    Points
    222
    Level
    2

    Re: Verilog and VHDL noise modelling

    Quote Originally Posted by FvM View Post
    Your question isn't very specific, what do you want to achieve?

    VHDL and Verilog are digital simulators without means to represent analog signals or sources.

    I can imagine a discrete noise generator as part of a digital signal processing test bench, it could e.g. use the pseudo random function UNIFORM() in IEEE.MATH_REAL and possibly digital filters for spectral shaping.
    You are right. But what I want to know, what are the possibilities to represent different types of noise sources using even mixed signal languages like VHDL-AMS, Verilog-A(AMS). To build a system model for example.



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 9,423, Level: 23

    Join Date
    Apr 2016
    Posts
    1,959
    Helped
    347 / 347
    Points
    9,423
    Level
    23

    Re: Verilog and VHDL noise modelling

    in theory, verilog/vhdl can be used just like a programming language and you can model anything you want.

    i think the real questions is whether these languages are good for this purpose. I would argue that no, they are not. if you need system-level model, matlab is probably a much better fit.
    Really, I am not Sam.


    1 members found this post helpful.

  5. #5
    Junior Member level 1
    Points: 222, Level: 2

    Join Date
    Oct 2019
    Posts
    19
    Helped
    5 / 5
    Points
    222
    Level
    2

    Re: Verilog and VHDL noise modelling

    Quote Originally Posted by ThisIsNotSam View Post
    in theory, verilog/vhdl can be used just like a programming language and you can model anything you want.

    i think the real questions is whether these languages are good for this purpose. I would argue that no, they are not. if you need system-level model, matlab is probably a much better fit.
    Thanks for your reply. If someone does not have Matlab license, which methodology is suitable in your opinion for system modelling of noise and/or component mismatch? The available tools are Cadence Spectre/AMS



    •   AltAdvertisement

        
       

  6. #6
    Advanced Member level 5
    Points: 9,423, Level: 23

    Join Date
    Apr 2016
    Posts
    1,959
    Helped
    347 / 347
    Points
    9,423
    Level
    23

    Re: Verilog and VHDL noise modelling

    if you don't have access to matlab, get octave.

    I still don't understand what you actually have as a system and why you insist on using a low level simulator. do you actually have a circuit with a certain topology? what is your application?
    Really, I am not Sam.


    1 members found this post helpful.

--[[ ]]--