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Why do we need a power splitted transistor ? (Analog layout)

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94d33m

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I heard in advanced nodes where the voltage is very low, if we share the VDD diffusion with two transistors , we can have an IR issue. But why is this ? Isnt the voltage same regardless of whether we share the diffusion or not ?
 

Hey,

I assume it has to do with what would happen if some (leakage) current is flowing through that diffusion. You know, current flowing through a diffused region of a semiconductor does not always flow where you would intuitively think it would flow.
For instance, take the base of a bipolar transistor. As soon as there is base-emitter current flowing, there might (will) happen something to the collector also, despite collector to base being reverse biased.

So if there is current flowing through the VDD diffusion because of one of the two transistors, some carriers might reach/influence the other transistor and unintended things might happen.
 

Some advanced nodes have very poor via qualities,
and it might be possible for a pair of transistors (or
a Vdd finger) to pass more current than some
interconnect feature(s) can stand reliably.

I am engaged on a project now where the foundry
models have substantial disagreement with what you
see if you try to pull your own curves, the foundry
says it's because of the high series resistance in the
fin contacts / vias which they "took care of" in their
model extraction, but appear in real material.
 

Shared diffusions are used everywhere, even in very advanced nodes (such as 7nm or 5nm), so it's not a universal rule.

Indeed, what you say makes some sense.
When a diffusion area is shared, the metal interconnects connected to that diffusion area carry double the current (as compared to one transistor case).
These interconnects have high resistance (contacts, vias, local interconnects, etc. - representing in CAD flow a very complex, 3D structure of the epitaxial diffusions for source/drain).
That high resistance leads to high voltage drop (metal debiasing), which is worse in advanced nodes because VDD is much lower there than in older nodes.
On the source side, the voltage drop leads to higher Vs and hence lower effective gate voltage Vgs=Vg-Vs.

For the same reason, the edge fingers of multi-finger devices (with shared source/drain regions) see lower IR drop, and hence conduct higher current - which leads to a nonlinear increase in current with increasing number of fingers - very few people realize this. A source of common problems for high-precision current sources and circuits based on them, such as current steering DAC.

- - - Updated - - -

I am engaged on a project now where the foundry
models have substantial disagreement with what you
see if you try to pull your own curves, the foundry
says it's because of the high series resistance in the
fin contacts / vias which they "took care of" in their
model extraction, but appear in real material.

If you do RC extraction, you may see a much better agreement with the measurements, as compared to schematic level (presim) simulations.

Often, foundries provide some guardbanding in their compact models, to make devices look worse than they really are, to guardband against inevitable process variation and other variables and unknowns.
Also, the interconnects on the test structures are adding high parasitics, whic are not accurately accounted for in schematic SPICE models.
 

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