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VHDL functions mistakes?

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clros

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Hi to all,

Ok, I have discovered that a my function work when I do:

Code: 
function myConvert (A : in STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ) return integer is
variable output : integer := 0;
begin
output := 5;
return output;
end function;

But, it do not work when I do:
Code: 
function myConvert (A : in STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ) return integer is
variable output : integer := 0;
begin
if a(7 downto 6) = "00" then
Output := 1;
elsif a(7 downto 6) = "01" then
Output := 2 ;
end if;
return output;
end function;

I do not understand... what is wrong?
 

I dont understand what counts as "work" and "do not work". The two functions are different, and syntactically fine. So whats the problem?
 

TrickyDicky said:
I dont understand what counts as "work" and "do not work". The two functions are different, and syntactically fine. So whats the problem?
Click to expand...

The second function return always zero.
 

Then clearly that the A input bits (7 downto 6) are not "00" or "01"
 

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