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Creating Verilog wrapper around a system Verilog DDR4 memory model from micron

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Dude99

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Recently downloaded a memory model for DDR4 memory from micron's website and found that they have converted their models into System Verilog Interfaces.
I'm ok with that... however, I still need to put a wrapper around it to make it work with mixed VHDL/Verilog-2001 simulation. I'm not really sure how to correctly connect the inout ports from the system Verilog interface to the inout port on the Verilog module. (see below) 

Code Verilog - [expand]
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// blasting the system interface because Verilog and VHDL doesn't support them...
module ddr4_module_wrapper(
    input logic[1:0]                          CK,
    input logic                               ACT_n,
    input logic                               RAS_n_A16,
    input logic                               CAS_n_A15,
    input logic                               WE_n_A14,
    input logic                               ALERT_n,
    input logic                               PARITY,
    input logic                               RESET_n,
    input logic                               TEN,
    input logic                               CS_n,
    input logic                               CKE,
    input logic                               ODT,
    input logic[MAX_RANK_BITS-1:0]            C,
    input logic[MAX_BANK_GROUP_BITS-1:0]      BG,
    input logic[MAX_BANK_BITS-1:0]            BA,
    input logic[13:0]                         ADDR,
    input logic                               ADDR_17,
    input wire[CONFIGURED_DM_BITS-1:0]        DM_n,
    
    inout wire[CONFIGURED_DQ_BITS-1:0]        DQ,
    inout wire[CONFIGURED_DQS_BITS-1:0]       DQS_t,
    inout wire[CONFIGURED_DQS_BITS-1:0]       DQS_c,
    
    input  logic                              ZQ,
    input  logic                              PWR,
    input  logic                              VREF_CA,
    input  logic                              VREF_DQ,
);
 
    parameter int           CONFIGURED_DQ_BITS  = 16;
    parameter int           CONFIGURED_RANKS    = 1;
    parameter UTYPE_density CONFIGURED_DENSITY  = _4G;
    
    DDR4_if #(.CONFIGURED_DQ_BITS(CONFIGURED_DQ_BITS)) iDDR4();
 
   //micron's ddr4 system Verilog model
    ddr4_model #(
        .CONFIGURED_DQ_BITS (CONFIGURED_DQ_BITS), 
        .CONFIGURED_DENSITY (CONFIGURED_DENSITY), 
        .CONFIGURED_RANKS   (CONFIGURED_RANKS)
    ) 
    ddr4_model (
        .model_enable       (1'b1), 
        .iDDR4              (ddr4)   // here we have a single interface for ddr4 ports
    );
 
       // here's the part I don't know... how to connect the inout interface ports to the inout ports of this Verilog wrapper module?
 
[B] //????? how to handle inout signals????
    assign ddr4_bus.DQ          = DQ;
    assign DQ                   = ddr4_bus.DQ;
 
    //????? how to handle inout signals????
    assign ddr4_bus.DQS_t       = DQS_t;
    assign DQS_t                = ddr4_bus.DQS_t;
    
    //????? how to handle inout signals????
    assign ddr4_bus.DQS_c       = DQS_c;
    assign DQS_c                = ddr4_bus.DQS_c;[/B]
    
// pure input signals are a piece of cake...
    assign ddr4_bus.CK           = CK;
    assign ddr4_bus.ACT_n        = ACT_n;
    assign ddr4_bus.RAS_n_A16    = RAS_n_A16;
    assign ddr4_bus.CAS_n_A15    = CAS_n_A15;
    assign ddr4_bus.WE_n_A14     = WE_n_A14;
    assign ddr4_bus.ALERT_n      = ALERT_n;
    assign ddr4_bus.PARITY       = PARITY;
    assign ddr4_bus.RESET_n      = RESET_n;
    assign ddr4_bus.TEN          = TEN;
    assign ddr4_bus.CS_n         = CS_n; 
    assign ddr4_bus.CKE          = CKE;
    assign ddr4_bus.ODT          = ODT;
    assign ddr4_bus.C               = C;
    assign ddr4_bus.BG              = BG;
    assign ddr4_bus.BA              = BA;
    assign ddr4_bus.ADDR         = ADDR;
    assign ddr4_bus.ADDR_17      = ADDR_17;   
    assign ddr4_bus.DM_n         = DM_n;
    assign ddr4_bus.ZQ           = ZQ;
    assign ddr4_bus.PWR          = PWR;
    assign ddr4_bus.VREF_CA      = VREF_CA;
    assign ddr4_bus.VREF_DQ      = VREF_DQ; 
    
endmodule;


Here's the interface connected to the system Verilog model from micron:

Code Verilog - [expand]
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interface DDR4_if #(parameter CONFIGURED_DQ_BITS = 8) ();
    import arch_package::*;
 
    parameter CONFIGURED_DQS_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
    parameter CONFIGURED_DM_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
 
    logic[1:0] CK; // CK[0]==CK_c CK[1]==CK_t
    logic ACT_n;
    logic RAS_n_A16;
    logic CAS_n_A15;
    logic WE_n_A14;
    logic ALERT_n;
    logic PARITY;
    logic RESET_n;
    logic TEN;
    logic CS_n;
    logic CKE;
    logic ODT;
    logic[MAX_RANK_BITS-1:0] C;
    logic[MAX_BANK_GROUP_BITS-1:0] BG;
    logic[MAX_BANK_BITS-1:0] BA;
    logic[13:0] ADDR;
    logic ADDR_17;
    wire[CONFIGURED_DM_BITS-1:0] DM_n;
    wire[CONFIGURED_DQ_BITS-1:0] DQ;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_t;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_c;
    logic ZQ;
    logic PWR;
    logic VREF_CA;
    logic VREF_DQ;
endinterface


Nice of them not to include any modports in the system Verilog interface to specify the port directions... well... we all known DDR has a few inouts from the specification for DDR4 memories...
 
Last edited by a moderator:

You can use port declaration expressions.

Code: 
module ddr4_module_wrapper(
   input .CK(ddr4_bus.CK),
   ...
   inout .DQ(ddr4_bus.DQ),
   ...
);
 

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