EEPuppyPuppy
Junior Member level 3
Hi, Hope anyone could help me.
About the circuit:
I am working on a circuit which is similar to SRAM but more complex, but it performs kinds of the same way.
The basic storage unit (or call it circuit) has write-line, read-line, and bit-line.
During writing process:
Write-line is ON and read-line is OFF. The value needed to be stored into the unit will be input from the bit-line.
During reading process:
White-line is OFF and read-line is ON. The value need to be the output from the unit will go out through the bit-line.
=========I have tried and my thoughts===============
I have done the simulation on a single unit with RC extraction and it works fine.
Since I don't know how to make the node (bit-line) be an input node for the first stage (writing) and be an output node for the second stage (reading), what I was doing is to do separate simulation for writing and reading.
Specifically for the reading process, I set an initial voltage (value) at the nodes in the circuit which store the values, which is the nodes connect to the investors. I found those storage nodes by comparing the skematic from Cadence and the HSpice netlist generated from Cadence.
This approach seems OK for a single unit simulation, but I need to do a simulation on a column which contains many of this single unitd.
1. If I draw the column circuit in Cadence and generate the whole circuit, there will be no subcircuit. And it is almost impossible for me to find all the storage nodes from the netlist due to the complexity of the schematic and the netlist. Even if I can, there is a very high risk of mistakes.
2. If I use the single unit as sub-circuit and make up the HSpice netlist file from it, I have no idea how to access those storage nodes from the sub-circuits and give them initial values.
I have tried another way which is adding extra input pins to the storage nodes which could let me have access to those storages nodes from the sub-circuits. But I realized that to make it work, I have to add extra capacitor to the pins I add to make the storage nodes could hold the values after the writing process. (Since I made slightly change on the unit by adding thoese pins, I ran the full simulation including writing and reading to make sure it works identical to the original unit circuit. When there are no capacitors added to the storage pins, in some cases, they could not hold the values and the same pins always go down to ZERO, and the other pins go up to ONE no mater what the correct values are.) So I believe that this adding-pin method eventually make the circuit works kinds of different from the original one, which might lead to wired output.
============Need Help==============
I have searched online and did not find any luck.
Could anyone let me know that is there a way in HSpice I could access the nodes from sub-circuit and give them initial values?
OR
Is there a way in HSpice to make a pin be an input for a period of time and make it an output for another period of time during one simulation run?
Thank you so much. Really appreciate your help.
About the circuit:
I am working on a circuit which is similar to SRAM but more complex, but it performs kinds of the same way.
The basic storage unit (or call it circuit) has write-line, read-line, and bit-line.
During writing process:
Write-line is ON and read-line is OFF. The value needed to be stored into the unit will be input from the bit-line.
During reading process:
White-line is OFF and read-line is ON. The value need to be the output from the unit will go out through the bit-line.
=========I have tried and my thoughts===============
I have done the simulation on a single unit with RC extraction and it works fine.
Since I don't know how to make the node (bit-line) be an input node for the first stage (writing) and be an output node for the second stage (reading), what I was doing is to do separate simulation for writing and reading.
Specifically for the reading process, I set an initial voltage (value) at the nodes in the circuit which store the values, which is the nodes connect to the investors. I found those storage nodes by comparing the skematic from Cadence and the HSpice netlist generated from Cadence.
This approach seems OK for a single unit simulation, but I need to do a simulation on a column which contains many of this single unitd.
1. If I draw the column circuit in Cadence and generate the whole circuit, there will be no subcircuit. And it is almost impossible for me to find all the storage nodes from the netlist due to the complexity of the schematic and the netlist. Even if I can, there is a very high risk of mistakes.
2. If I use the single unit as sub-circuit and make up the HSpice netlist file from it, I have no idea how to access those storage nodes from the sub-circuits and give them initial values.
I have tried another way which is adding extra input pins to the storage nodes which could let me have access to those storages nodes from the sub-circuits. But I realized that to make it work, I have to add extra capacitor to the pins I add to make the storage nodes could hold the values after the writing process. (Since I made slightly change on the unit by adding thoese pins, I ran the full simulation including writing and reading to make sure it works identical to the original unit circuit. When there are no capacitors added to the storage pins, in some cases, they could not hold the values and the same pins always go down to ZERO, and the other pins go up to ONE no mater what the correct values are.) So I believe that this adding-pin method eventually make the circuit works kinds of different from the original one, which might lead to wired output.
============Need Help==============
I have searched online and did not find any luck.
Could anyone let me know that is there a way in HSpice I could access the nodes from sub-circuit and give them initial values?
OR
Is there a way in HSpice to make a pin be an input for a period of time and make it an output for another period of time during one simulation run?
Thank you so much. Really appreciate your help.