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How to do post layout simulation during digital ASIC design?

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daskk62

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I want to design a 16-bit up-down counter ASIC. For that firstly I wrote the verilog code for 16-bit up-down counter and synthesized using Cadence genus tool. And Layout is made using cadence Innovus tool. Now I want to check the simulation based result of the layout. How can I check the simulation result of the layout.

For Analog design I did the post layout simulation, where the tool I have used is cadence Virtuoso. And the post layout simulation I obtained after PEX. In digital design how can I do the post layout/netlist simulation.
 

How did you make the simulation for the original verilog code?
It should be the same, but you need to first compile the standard cells library file then compile the output netlist from the layout tool. Also note that you may not see internal signals of the block because the netlist may have optimized things and removed unneeded signals
 

How did you make the simulation for the original verilog code?
It should be the same, but you need to first compile the standard cells library file then compile the output netlist from the layout tool. Also note that you may not see internal signals of the block because the netlist may have optimized things and removed unneeded signals

For original verilog code the simulation is performed using vivado simulator.
My question is inside the Cadence Innovus tool is there any option to perform the layout simulation, since the layout is made using Cadence innovus tool.
Or I need to shift to other tool like cadence virtuoso?
 

digital is not analog. there is no such thing as post layout simulation. design sizes are huge, simulators choke on them.

you have to think about what you are trying to achieve here. meet timing? there is sta for that. power assessment? there is extraction and power reporting builtin in innovus.
 

Generally speaking, you would take the design netlist (which will be your DUT) and instantiate it within your testbench (the same top-level testbech that was used during functional verification), that's it!
For digital designs Cadence NCSim is used.
 

Generally speaking, you would take the design netlist (which will be your DUT) and instantiate it within your testbench (the same top-level testbech that was used during functional verification), that's it!
Well that, and then annotating with SDF so that it has post-layout timing information.

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digital is not analog. there is no such thing as post layout simulation. design sizes are huge, simulators choke on them.
There is, but for pure digital, it's typically post-layout gate-level with SDF based on extracted RC, rather than transistor level simulation.

You can do transistor level simulation for small digital circuits too - just make sure you're using a fast spice sim that is optimised for the task, like CustomSim, rather than the regular spectre/hspice. 99.9% of the time you wouldn't need to do this - but you might if you're doing some mixed-signal stuff.
 

my point is that I have never heard anyone referring to it as post layout simulation. we say annotated gate level simulation.

and the closest I have seen people doing is hspice of critical paths, sometimes for validation or chasing that sweet last picosecond in your STA.
 

And the post layout simulation I obtained after PEX. In digital design how can I do the post layout/netlist simulation.

Do the final layout in a Physical Design tool (i.e. Cadence Innovus). Extract the parasitics for the interconnects in spef (or dspf) format along with the timing for the specific corner in .sdf format. The gate level parsitics are already available in your STD_LIB (.db) files. Then use an STA too like PrimeTime for post layout simulation. What differs from a normal gate-level simulation here, is the interconnect parasitics you load from .spef file to PrimeTime. This will give you a good estimation (but won't be as accurate as transistor level simulation in Virtuoso).

Anuradha
 

Generally speaking, you would take the design netlist (which will be your DUT) and instantiate it within your testbench (the same top-level testbech that was used during functional verification), that's it!
For digital designs Cadence NCSim is used.
Sorry for the late reply.
I have some questions (1) cadence NCSim and Cadence incisive enterprise simulator are they same?
(2) As you said I can use cadence NCsim for post place and route netlist simulation for my ASIC. Can I use the same NCsim simulator for the purpose of FPGA simulation.
 

1 - incisive is the family of tools, ncsim is a simulator of that family.
2 - technically, yes, it is possible. but it is hardly a good idea as you can do that much much easier in an FPGA specific toolset.
 

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