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Verilog with multiple if conditions

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techy5025

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I am using an if statement with multiple conditionals. Is there a shortcut way to write this as the "year_rt" is the same in each case .. but the condition is different. This is used in a string of "if" statements that doesn't lend itself well to using the "case" statement.


Code:
 if ((year_rt == 06) || (year_rt == 17) || (year_rt == 23))
      begin
          calendar <= 1;               // Month starts on Sunday
          leap <= 0;                    // .. no leap year
      end

Thanks,
Jim
 

Hi,

You could look for a mathematical formula
Or use a table

Klaus
 

case statement is the most compact way to write the multiple comparison:

Code Verilog - [expand]
1
2
3
4
5
6
7
case (year_rt)
   6, 17, 23:
      begin
          calendar <= 1;               // Month starts on Sunday
          leap <= 0;                    // .. no leap year
      end
 endcase



System Verilog inside operator could be also used, if supported by your tool.
 

Thanks for the reply's! I am a newby to verilog and am trying to get familiar with the syntax and structure. I thought use of the "case" statement required that the "cases" be sequential .. as in 1,2,3,4. Every example I have seen was like that .. obviously not. I will recode .. and look for the "inside" operator. Lots to learn!

Thanks again,

Jim
 

Code:
calendar <= some value;               // Month starts on Sunday
leap <= some value;                    // .. no leap year
case(year_rt)
    6,17,23:
      begin
          calendar <= 1;               // Month starts on Sunday
          leap <= 0;                    // .. no leap year
      end   
endcase
This kind of coding can avoid latch.
 

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