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Great difference between ADS simulation and Cadence simulation

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OZZAA

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I am desinging an amplifier (Class_C) at 5 GHz, using (TSMC 180nm)
I designed it using ADS simulstor and the following figure describes the relation between input and output power.
Untitled_2.png
while the same circuit is designed at Cadence and it gives a great differences between these two circuits, as follows.
Untitled_1.png
I think I made some thing wrong.
what is the wrong for this desinged circuit to make such these differences.
is that for the properties of used ports.
Untitled.png
 

What do you mean by Cadence ?
Use correct terminolgy,

If you mean Cadence Spectre, show me netlist for both ADSsim and Spectre.
 

Yes Cadence 5 (Spectre).
do you mean by netlist is the designed circuit of ADS?
 

Last edited:
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    OZZAA

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It is solved,
Thanks for your interest.
However the ADS program gives me that warning
Untitled.png
what it is meaning about these warning especially the highlighted line
 

It is solved
Simply your circuit or device model is not same between ADSsim and Spectre.
That’s all.

Show me netlist for both ADSsim and Spectre.

What analysis do you apply in ADSsim and Spectre ?
Do you use HB for ADSsim and Shooting-Newton-PSS or HB-PSS for Spectre ?

Transient Analysis of Spectre also shows similar warnings as ADSsim.

Show me netlist for both ADSsim and Spectre.
 
Last edited:

ADS netlist
Options ResourceUsage=yes UseNutmegFormat=no EnableOptim=no TopDesignName="PA3_lib:Test5_FullPA_Optimization_v6:schematic" DcopOutputNodeVoltages=yes DcopOutputPinCurrents=yes DcopOutputAllSweepPoints=no DcopOutputDcopType=0
; Library Name: PA3_lib
; Cell Name: 5 SecondStage_v6
; View Name: schematic
define "5#20SecondStage_v6" ( P1 P2 )
;parameters
L:L3 P1 0 L=1.331216 nH R=1e-12 Ohm Noise=yes
C:C3 P1 vg C=7.268545 pF
L:L2 P2 0 L=1.277087 nH R=1e-12 Ohm Noise=yes
C:C2 vd P2 C=5.308445 pF
simulator lang=ads

Vdd2=1.8
Vgg21=0.3 tune{ -0.1 to 1 by 0.1 }
V_Source:SRC3 Vgg21 0 Type="V_DC" Vdc=Vgg21 V SaveCurrent=1
"nmos_rf":M1 vd vg 0 0 lr=0.18 um wr=8 um nr=64
V_Source:SRC1 Vdd2 0 Type="V_DC" Vdc=Vdd2 V SaveCurrent=1
R:R2 Vgg21 vg R=1 kOhm Noise=yes
Short:Idc N__4 vd Mode=0 SaveCurrent=yes
L:L1 Vdd2 N__4 L=0.51 nH Noise=yes
C:C1 0 vd C=2 pF
end "5#20SecondStage_v6"

Tran:Tran1 StartTime=1 nsec StopTime=1.5 nsec MaxTimeStep=1.0 nsec LimitStepForTL=yes TimeStepControl=2 TruncTol=7.0 ChargeTol=1.0e-14 IntegMethod=0 MaxGearOrder=2 \
Mu=0.5 MaxOrder=4 Freq[1]=1.0 GHz Order[1]=3 HB_Window=no \
HB_Sol=no ImpApprox=no ShortTL_Delay=1.0 psec ImpMode=1 UseInitCond=no \
LoadGminDC=no CheckKCL=yes CheckOnlyDeltaV=yes OverloadAlert=no DeviceBypass=no \
MaxIters=10 MaxItersDC=200 DevOpPtLevel=0 StatusLevel=2 OutputAllPoints=yes \
NoiseScale=1 ImpEnforcePassivity=yes \
OutputPlan="Tran1_Output"

OutputPlan:Tran1_Output \
Type="Output" \
UseNodeNestLevel=yes \
NodeNestLevel=2 \
UseEquationNestLevel=yes \
EquationNestLevel=2 \
UseSavedEquationNestLevel=yes \
SavedEquationNestLevel=2 \
UseDeviceCurrentNestLevel=no \
DeviceCurrentNestLevel=0 \
DeviceCurrentDeviceType="All" \
DeviceCurrentSymSyntax=yes \
UseCurrentNestLevel=yes \
CurrentNestLevel=999 \
UseDeviceVoltageNestLevel=no \
DeviceVoltageNestLevel=0 \
DeviceVoltageDeviceType="All"

"5#20SecondStage_v6":X1 N__4 N__6
S_Param:SP2 CalcS=yes CalcY=no CalcZ=no GroupDelayAperture=1e-4 FreqConversion=no FreqConversionPort=1 StatusLevel=2 CalcNoise=no SortNoise=0 BandwidthForNoise=1.0 Hz DevOpPtLevel=0 \
SweepVar="freq" SweepPlan="SP2_stim" OutputPlan="SP2_Output"

SweepPlan: SP2_stim Start=1 GHz Stop=20 GHz Step=0.5 GHz

OutputPlan:SP2_Output \
Type="Output" \
UseEquationNestLevel=yes \
EquationNestLevel=2 \
UseSavedEquationNestLevel=yes \
SavedEquationNestLevel=2

#load "python","LinearCollapse"
Component Module="LinearCollapse" Type="ModelExtractor" NetworkRepresentation=2
Port:Term3 vout 0 Num=2 Z=50 Ohm Noise=yes
Port:pORT1 vin 0 Num=1 Z=50 Ohm P[1]=dbmtow(Pavs) Freq[1]=RFfreq Noise=yes Pac=polar(dbmtow(0),0)
Short:Iload N__6 vout Mode=0 SaveCurrent=yes
Short:Iin vin N__4 Mode=0 SaveCurrent=yes
HB:HB1 MaxOrder=4 Freq[1]=RFfreq Order[1]=3 StatusLevel=2 SweepVar="Pavs" SweepPlan="HB1_stim" OutputPlan="HB1_Output"

SweepPlan: HB1_stim Start=-5 Stop=20 Step=1

OutputPlan:HB1_Output \
Type="Output" \
UseNodeNestLevel=yes \
NodeNestLevel=2 \
UseEquationNestLevel=yes \
EquationNestLevel=2 \
UseSavedEquationNestLevel=yes \
SavedEquationNestLevel=2 \
UseDeviceCurrentNestLevel=no \
DeviceCurrentNestLevel=0 \
DeviceCurrentDeviceType="All" \
DeviceCurrentSymSyntax=yes \
UseCurrentNestLevel=yes \
CurrentNestLevel=999 \
UseDeviceVoltageNestLevel=no \
DeviceVoltageNestLevel=0 \
DeviceVoltageDeviceType="All"

Tran:HB1_tran HB_Sol=1 SteadyState=1 StatusLevel=3 \
Freq[1]=RFfreq Order[1]=3

Component:tahb_HB1 Module="ATAHB" Type="ModelExtractor" \
Tran_Analysis="HB1_tran" HB_Analysis="HB1"


Pavs=5
RFfreq=5 GHz tune{ 1 GHz to 36 GHz by 1 GHz }

Spectre netlist
C2 (net11 net3 0) mimcap_shield lt=29.5u wt=29.2u m=8
C1 (net30 0 0) mimcap_shield lt=30u wt=30u m=2
C0 (net30 net16 0) mimcap_shield lt=30u wt=27.85u m=5
L2 (net16 0 0) spiral_s2_std w=6u nr=2.5 rad=44.0u lay=6 m=1
L1 (net3 0 0) spiral_s2_std w=6u nr=2.5 rad=45.8u lay=6 m=1
L0 (Vdd net30 0) spiral_s2_std w=6u nr=1.5 rad=34.8u lay=6 m=1
PORT2 (net16 0) port r=50 num=2 type=dc freq=fin dbm=pin \
fundname="rf_freq"
PORT1 (net3 0) port r=50 num=1 type=sine freq=fin dbm=pin \
fundname="rf_freq"
V1 (Vgg 0) vsource dc=300.0m type=dc
V0 (Vdd 0) vsource dc=1.8 type=dc
R0 (Vgg net11 0) rppolywo_rf l=6u w=2u mf=(1)
M0 (net30 net11 0 0) nch l=180.0n w=8u m=64 ad=2.16e-12 as=2.2125e-12 \
pd=8.54u ps=8.80313u nrd=0.03375 nrs=0.03375
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
sweeppss sweep param=pin start=-5 stop=10 step=5 {
pss pss fund=5G harms=5 errpreset=moderate annotate=status

}

modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save PORT1:p PORT2:p
saveOptions options save=allpub
that's it
so why the error in my previous comment always appears.
 

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