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Im using 2 cascaded CML D latches in order to implement the CML D Flip flop. Can you please explain a bit more how to configure the slave e.g as an OR gate?
That's the flattened master-slave configuration. 2 latches cascaded
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Which feedback path do you mean? According to the image below, this should be the schematic of a DFF using master-slave latches.
Also, through simulation it seems to behave correctly
So you mean in the second latch ( slave latch e.g ) , add also input for SET and SETbar in OR configuration?
Or instead of a second latch , use an OR gate?
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