reservevoltage
Newbie level 4
Hello,
I have a demo card named cpld c-m240 epm240t100c5n.
I tried to send the data with uart and have a synchronous problem. (ı think)
According to my basic information in Uart communication, the duration of 1 or 0 for each bit (at 9600 baudrat and 50Mhz clok) is 104us.
I divided the 50Mhz to 9600 and created a counter according to the result.
Unfortunately ı could not figure out test bench logic. That is why the code is running without a simulation.
I had realized differences between sended byte and described byte at code when ı read the sended value from realterm.
My code is below. Does anyone hava a suggestion?
I have a demo card named cpld c-m240 epm240t100c5n.
I tried to send the data with uart and have a synchronous problem. (ı think)
According to my basic information in Uart communication, the duration of 1 or 0 for each bit (at 9600 baudrat and 50Mhz clok) is 104us.
I divided the 50Mhz to 9600 and created a counter according to the result.
Unfortunately ı could not figure out test bench logic. That is why the code is running without a simulation.
I had realized differences between sended byte and described byte at code when ı read the sended value from realterm.
My code is below. Does anyone hava a suggestion?
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity main is
Generic (
CLK_FREKANS : integer := 50000000;
BAUDRATE : integer := 9600
);
Port(
in_clk : in std_logic;
in_rst : in std_logic;
in_tx_start : in std_logic;
in_tx_data : in std_logic_vector(7 downto 0):="10101010";--sended data
out_tx : out std_logic;
out_tx_ok : out std_logic
);
end main;
architecture Behavioral of main is
constant CLK_BIT : integer := (CLK_FREKANS / BAUDRATE);--5208
type t_UART_tx is (IDLE, START_B, SEND_D, STOP_D, Transmit_OK);
signal r_UART_tx : t_UART_tx := IDLE;
signal r_clk_counter : integer range 0 to CLK_BIT-1 := 0; -- 0 to 5207
signal r_data_ind : integer range 0 to 7 := 0;
signal r_data : std_logic_vector(7 downto 0) := (others => '0');
signal r_tx : std_logic := '1';
signal r_tx_ok : std_logic := '0';
signal counter: integer range 0 to 96000:=0;
begin
out_tx <= r_tx;
out_tx_ok <= r_tx_ok;
process(in_clk, in_rst)
begin
if in_rst = '1' then
r_UART_tx <= IDLE;
r_clk_counter <= 0;
r_data_ind <= 0;
r_data <= (others => '0');
r_tx <= '1';
r_tx_ok <= '0';
elsif rising_edge(in_clk) then
r_tx_ok <= '0';
case r_UART_tx is
--------------------------------------------------------------
when IDLE =>
--r_tx <= '1';
r_clk_counter <= 0;
r_data_ind <= 0;
if in_tx_start = '1' then
r_data <= in_tx_data;
r_UART_tx <= START_B;
end if;
--------------------------------------------------------------
when START_B =>
if r_clk_counter = CLK_BIT then --=5207
r_clk_counter <= 0;
r_tx <= '0';
r_UART_tx <= SEND_D;
else
r_clk_counter <= r_clk_counter + 1;
end if;
--------------------------------------------------------------
when SEND_D =>
if r_clk_counter = CLK_BIT then --=5207
r_clk_counter <= 0;
r_tx <= r_data(r_data_ind);
if r_data_ind = 7 then
r_data_ind <= 0;
r_UART_tx <= STOP_D;
else
r_data_ind <= r_data_ind + 1;
end if;
else
r_clk_counter <= r_clk_counter + 1;
end if;
--------------------------------------------------------------
when STOP_D =>
if r_clk_counter = CLK_BIT then --=5207--=5207
r_clk_counter <= 0;
r_tx <= '1';
--r_UART_tx <= Transmit_OK;
if counter=96000 then
r_UART_tx <= Transmit_OK;
else
counter<=counter+1;
end if;
else
r_clk_counter <= r_clk_counter + 1;
end if;
--------------------------------------------------------------
when Transmit_OK =>
r_tx <= '1';
r_tx_ok <= '1';
r_UART_tx <= IDLE;
when others => NULL;
end case;
end if;
end process;
end Behavioral;