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UGBW not achieved in opamp

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fat_123

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hello,

i have designed 32nm bsim bulk cmos 2-stage opamp.

and i have considered specification:
UGBW=19MHz, CL=5pF, Cc=1.24pF, Current= 7uA,

But i am getting a lower UGBW i.e. 13 or 15MHz, Is it acceptable?
i have increased width of all the transistors but not getting 19MHz BW.
what i am supposed to do?
 

What are you comparing? Real hardware versus simulation? Simulation versus text book calculation? Or?
 

There are many things you have to look at. For example, what is the gm of the 1st stage, where is the non-dominant pole, is your operating point correct as expected, etc.
 

What are you comparing? Real hardware versus simulation? Simulation versus text book calculation? Or?

I am comparing my calculation with simulation

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There are many things you have to look at. For example, what is the gm of the 1st stage, where is the non-dominant pole, is your operating point correct as expected, etc.

could you tell me more how to correct it
 

Not unless you tell us all the things that are needed for that.
 

crkt.png

this is the circuit. i did gm/id technique and calculated its width and length.
but after designing i am not getting a required UGBW.
may be it happens with CMOS at lower technology?

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and also PSRR is troubling.

i am getting lower value of PSRR than DC gain

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and how to take a bias point to get required gain and BW

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one more thing,
which parameter should i give importance to
that means: if i increase bias voltage, dc gain and UGBW increases but PM decreases
and when i reduce bias voltage, dc gain and UGBW reduces and PM increases

so how to set the bias voltage?

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PM= Phase Margin
 

13MHz compared to 19MHz is not a drastic difference.
Anyway, you should provide here the gm of M1/2, gm of M7. Would be good to know the operating point in general for the transistors.
Meanwhile try placing a resitor in series with Cc and make it something like 1/gm7. You may need to go around this value a bit. See if it helps.
 

i am gettin 11MHz so can i consider it fine?
 

No, because you have to understand where the discrepancy comes from. And if this amplifier is going to a larger system, you will also have to know if 11MHz is something you can live with.
 

because of technology scaling, short channel effects occur in cmos which deteriotes the performance of the circuit.
therefore we shift from cmos devices to other devices like finfet,tfet.

isn't it?
 

Not likely. First, you are using 32nm technology, which shouldn't have any problem with such a low frequency as 20MHz. Second, you are using carbon nanotubes transistors which should have pretty good intrinsic gain and you should not suffer from much of a grain-bandwidth trade-off. Third, you said you used the gm/Id method to design your circuit, which means you should be pretty much on the spot when you simulate and if you are not, you should be able to trace down the problem. Bottom line, you will have to understand where the problem is. Thing is, you won't be able to do that without looking at the transistor small signal parameters like gm, gds, Cgg, Cds. For that you need to have the DC operating point information.
 

no no i designed it for bsim 4 bulk CMOS 32nm technology
 

Well, it doesn't change much what I said before.
 

that means there is some problem in my design
i have taken gm/id of m1/m2 ==21.1 = (2*3.14*1.24pF*19MHz)/7uAgmid.png

gm7=1304 (2.2*gm1,2*CL/Cc)
 

If you work with gm/Id=21, you are already close to or inside weak inversion. But this is not what is needed. You need to get the real gm of M1 and M7 as they are reported from the OP information and not as you calculate it through gm/Id and your wanted UGBW.
Plus, I hope you didn't characterize your transistors for gm/Id using the method you just showed.
 

from .op command
M1 gm/id=18.5
m7 gm/id=17.84
 

OK, so is the tail current of the diff pair 7uA, or 7uA is the current per transistor? What is the current in the second stage?
 

Iref=7uA and m5 twice the size of m6 so m5 current will be 14uA and across differential amplifier 7uA
how can i find second stage current?
 

Well, it is the current in M8, the PMOS transistor in the second stage. What is M8 ratio to M6?
 

from .op command current in M8 is 31.55u
M8/M6= 3.9
 

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