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SAR ADC Architecture Blocks

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Adithya_Pai

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I am in the journey of understanding operation of data converters and in mean time I found SAR ADC fascinating. I have a question regarding charge redistribution DAC as given in this document

Screenshot_58.png

But TI slide 4 and 5 of this link provides different view CDAC block has comparator with positive connected to GND https://slideplayer.com/slide/14552041/

Screenshot_59.png

Screenshot_60.png
Query1 : Comparator output in CDAC in (second link) is digital Is it given to outer comp (slide 4) IF yes how is this operation achievable since all the process is done in CDAC itself.(VIN connected to CDAC is not shown in the block diagram)


How is this CDAC since it dosent justify generic working related to link 1 by analog devices?
 
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Actually, the TI link describes the traditional approach in building integrated SAR ADC with charge redistribution. The ADI link is a bit fuzzy to me since it doesn't even give an idea what is inside the DAC block.
Anyway, the comparator output is digital and it goes to the SAR logic. Everything happens internally. Basically, you sample the input on all CDAC caps. Then, the SAR logic starts reconfiguring the CDAC caps such that the comparator test for each bit of the ADC output. Based on your last figure, if the comparator says 1 it means Vin is bigger than the binary portion of Vref that it is being currently compared against. In this case the capacitor connected to Vref stays and the next LSB capacitor is connected also to Vref. Follows new comparison. If the comparator says 0, then the presently connected to Vref capacitor is disconnected from Vref and connected to gnd. The next LSB capacitor is connected to Vref and a new comparison follows. This procedure repeats until all capacitors in the CDAC are tested.
The configuration in the second figure differs from the one in the 3rd. In the second figure you sample Vin on a dedicated T/H and the DAC output is compared to that. At the end of the conversion the DAC output is within +/- 0.5*LSB from the sampled Vin.
In the 3rd figure, as I mentioned Vin is sampled on the CDAC itself and during the bit tests CDAC output is equal to a*Vref-Vin, where "a" can be 1/2, 3/4 or 1/4, 1/8 or 3/8 or 5/8 or 7/8, etc. depending on the path the binary search algorithm takes. At the end of the conversion CDAC output is within 0.5LSB away from 0V.
 

Best would be to read more about SAR ADC in textbooks:

Analog Integrated Circuit Design
by Tony Chan Carusone, David Johns, Kenneth Martin
 
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    t4_v

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Best would be to read more about SAR ADC in textbooks:

Analog Integrated Circuit Design
by Tony Chan Carusone, David Johns, Kenneth Martin

I agree. There are many resources where you may investigate approaches to SAR ADC. Baker should be good too.
 

For the ADI part:
It seems that on each cycle, charge is being dumped on the sampling capacitor and then it is being compared to Vdd/2. If the code is too high, the change is reverted and a smaller amount of charge is dumped and then the voltage is compared once again to Vdd/2.
For the TI part:
The difference is that the charge on the sampling capacitor is not touched. There is a cap bank that works off a reference voltage and in each cycle, different voltages are being generated using charge re-distribution in the cap bank. This voltage is compared to the input voltage and if it is too high, it is reverted.

For the ADI part, it is a 6 pin part and does not have a reference pin and therefore the onus is on the end user to provide a stable supply voltage. For the TI part, you would need to provide an external reference.

Maybe the other ADC designers here can shed more light into the difference between the two parts.
 

I don't think the ADI part dumps charge on the sampling capacitor during conversion. After sampling, the charge at the (+) input of the comparator is frozen, unless the DAC provides resistive path to either ref or gnd and thus change the total charge stored on that node. But it doesn't look that way. So, if the DAC is capacitive, it can only redistribute the charge at the comparator input among all caps attached to it, creating different voltages but the total charge acquired during sampling stays the same. Total charge is actually the signal.
 

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