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[SOLVED] comma in 'always' statements (Verilog HDL)

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PGPPG

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Hello,

Is it allowed to use comma(',') in 'always' statement?

I accidently used comma(',') instead of 'or' in 'always' statement when desining a clock generator in verilog HDL.

like this: always @(negedge RST, posedge CLK) begin ~ end

I'd like to ask whether using comma works differently from using 'or', and if it is different, how it is different.

Actually I didn't notice any unexpected operation during verificaiton of its operation.

Thank you.
PG
 

I'd like to ask whether using comma works differently from using 'or'
Same. However synthesized results might be different.

‘,’ is recommended, since inside ‘()’ is Sensitivity List.
 
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Thank you very much for your reply.

Waiting my question to be uploaded, I found a reference for your comment in IEEE standard of system Verilog 2017.

event or operator.PNG
- IEEE Standard for SystemVerilog-Univied Hardware Design, Specification, and Verification Language, p.218, 2017

Thank you so much.
PG
 

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