Post synthesis gate level simulation

Hello Forum,
I am working on gate level simulations for generating saif file for power estimation. I am running simulations on post ICC generated netlist and sdf file(generated from prime time using spef file extracted using star rc tool). In sdf file the min::max delays corresponds to the minimum and maximum delays of that path.

I am not doing any timing closure. So I am not worried about the timing violations. Although I have 3-4 violations only, which can be fixed using eco tool.

So when I run functional simulation on the netlist using the delays in the sdf file I observe the following pattern:

Corner 1: set up time passed and hold time failed(timing reports from prime time analysis). When I run functional simulation on the netlist by selecting max delays from the sdf file of this corner, the simulation output matched the pre synthesis simulation output. But when I simulated with the min delays (I expected it to output don't cares as the design has hold violations) surprisingly the output matched the pre synthesis simulation output.
Corner 2: set up time passed hold time failed. Post synthesis simulation results matched pre synthesis simulation results for max delays, got don't cares as outputs when I selected min delays for sdf back annotation from this corner's sdf.(results are as I expected)
Corner 3: set up time failed and hold time failed. Simulation results output don't cares for both min and max delays.(results are as I expected)

I have the following questions:
1) Can I expect the design which has hold time violations but no set up violations for a particular corner to give correct outputs (doing netlist simulation) when selected max delays from the sdf file of that corner?
2) I can not understand why for corner 1, when simulated with min delays in sdf file gave correct outputs although hold timing failed for this corner.

I can simply simulate the netlist without any delays and generate toggle rates. But I wanted to know whether my understanding about sdf file and gate level simulations is correct.

Can I expect the design which has hold time violations but no set up violations for a particular corner to give correct outputs (doing netlist simulation) when selected max delays from the sdf file of that corner?

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From my point of view, timing analysis tells you about how likely your circuit would work. You probably shouldn't make any assumption about what it didn't tell you. In your case::

1. If you are using min delay corner for hold time analysis; and you have hold time violations. Then, it doesn't guarantee your circuit will pass the max delay corner.
2. If you are using max delay corner for hold time analysis, then it tells you that your circuit would probably fail under the given circumstances.

In both case, it doesn't guarantee anything. It doesn't tell you whether your circuit would work or not.

I can not understand why for corner 1, when simulated with min delays in sdf file gave correct outputs although hold timing failed for this corner.

Click to expand...

As aforementioned, it doesn't guarantee your circuit would work; but it doesn't mean it won't work. You should check compare the simulation waveform with your STA report. What's told by your STA report might not reflect exactly the way your circuit behaves in the simulation. It could be the operating conditions, or the constraints given (e.g. in/output delays, uncertainties etc.).

The whole thing about STA is to make sure your circuit would work even at the worst case condition. Usually, we optimize the circuit to a point that we are really confident.