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Verilog code for ring counter using "Genvar"

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djc

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Hello all.
I am a beginner in verilog language. I wrote a code for ring counter using "genvar". But during compilations i am getting an error. I am using vim editor and Modelsim for simulations. Can anyone please spare some time and show me the right way.
Design code is
Code: 
module dff(d_in,q_o,clk,rst);
input clk,rst;
input d_in;
output reg q_o;

always@(posedge clk) begin
	if(rst) q_o <= 0;
	else q_o <= d_in;
end
endmodule

module ring_counter(d_in,q_o,clk,rst);

parameter N=4;
input clk,rst;
input d_in;
output reg [N-1:0] q_o;
assign d_in=q_o[N-1];
genvar i;
 
generate 
	for(i=0;i<N;i=i+1)begin
	dff inst_1(q_o[N-1],q_o[i],clk,rst);
	end
endgenerate
endmodule

Testbench code is
Code: 
`include "ring_conter_genvar.v"
module tb;
parameter N=4;
reg clk,rst;
reg d_in;
wire [N-1:0] q_o;
integer delay;

ring_counter #(.N(N)) dut(d_in,q_o,clk_rst);

initial begin
	clk=0;
	forever clk=~clk;
end

initial begin
repeat(20) begin

	delay = $urandom_range(5,30);

	#delay;

	d_in = $random;

end

end

initial begin
#200;
$finish;
end

endmodule

Error is
[CODE]
Loading work.tb
# Loading work.ring_counter
# Loading work.dff
# ** Warning: (vsim-3017) tb_ring_counter.v(9): [TFMPC] - Too few port connections. Expected 4, found 3.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut File: ring_conter_genvar.v
# ** Warning: (vsim-3722) tb_ring_counter.v(9): [TFMPC] - Missing connection for port 'rst'.
# ** Error (suppressible): (vsim-3053) ring_conter_genvar.v(23): Illegal output or inout port connection for port 'q_o'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut/genblk1[0]/inst_1 File: ring_conter_genvar.v
# ** Error (suppressible): (vsim-3053) ring_conter_genvar.v(23): Illegal output or inout port connection for port 'q_o'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut/genblk1[1]/inst_1 File: ring_conter_genvar.v
# ** Error (suppressible): (vsim-3053) ring_conter_genvar.v(23): Illegal output or inout port connection for port 'q_o'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut/genblk1[2]/inst_1 File: ring_conter_genvar.v
# ** Error (suppressible): (vsim-3053) ring_conter_genvar.v(23): Illegal output or inout port connection for port 'q_o'.
#    Time: 0 ns  Iteration: 0  Instance: /tb/dut/genblk1[3]/inst_1 File: ring_conter_genvar.v
# Error loading design

[/CODE]
 

I think your problem is your statement
q_n[N-1] in the generate block.

N is a constant, but it wants to be a variable.
 

Thank you for the reply sir,
If i may ask,Can you please suggest corrections for the same.
 

The easiest way to look at a for loop is to unroll it manually to make sure you wrote it correctly

Code Verilog - [expand]
1
2
3

for(i=0;i<N;i=i+1)begin
    dff inst_1(q_o[N-1],q_o[i],clk,rst);
    end


Code Verilog - [expand]
1
2
3
4

dff inst_1[0](q_o[3], q_o[0], clk, rst);
dff inst_1[1](q_o[3], q_o[1], clk, rst);
dff inst_1[2](q_o[3], q_o[2], clk, rst);
dff inst_1[3](q_o[3], q_o[3], clk, rst);


Notice anything wrong? i.e. the input to the DFF is always bit-3

Besides this your clock generation as written in your testbench won't work
Code Verilog - [expand]
1

forever clk =~clk;

will cause the simulator to reach an iteration limit and error out as there is no time control in that statement. You need to add a #Half_the_clock_period before the LHS of the assignment.
 
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    D

    djc

    Points: 2
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Thanx for the reply sir.

I edited the code as per your suggestion.
Sorry there is no symbol for wrapping the code.

Test bench code

`include "ring_conter_genvar.v"
module tb;
parameter N=4;
reg clk,rst;
reg d_in;
wire [N-1:0] q_o;
integer delay;

ring_counter #(.N(N)) dut(d_in,q_o,clk,rst);

initial begin
clk=0;
forever #5 clk=~clk;
end

initial begin

rst=1;
#20;
rst=0;

repeat(20) begin
delay = $urandom_range(5,30);
#delay;
//#5;
d_in = $random;
end

#200;
$finish;
end

initial begin
$monitor("Data=%d,q_o=%d",d_in,q_o);
end

endmodule
Click to expand...

I just wanted to make the code more generalized so that if needs to make it 8 digit so not much shouldn't be change in the design code. So I tried to use "genvar".
 

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