Artix7 XC7A100T BRAM Math

Hello dear gurus!

In Datasheet of Artyx7 XC7A100T has 270 18KB blocks

to save image frame from camera needed 9 830 400s (1280x960x8) bit but cannot make Bram IP, can save little more than 4 915 200s (1280x960x4) but

8x1024 is equal 1KB
8x1024x270 is equal 2 211 840bits
So
Saved 4 915 200bits more than Available 2 211 840 bits twice than data from Datasheet and this is strange .

I am not understand why it can fit ?

How do you actually know you are saving anything?

Also, you Can look at the utilization reports which will show exactly how much memory is used.

Hello, I know it, because it saves picture in bram and shows an image through vga. Canno find in Xilinx ISE

Why do you want to save 8 frames? usually for a standards converter you need only a couple of frames - one for read and one for write.

one pixel 8 bit, frame countless.

The XC7A100T has 270 18Kb blocks, that's 4976640 bits. I don't know where you got 2211840 bits.

barry said:

The XC7A100T has 270 18Kb blocks, that's 4976640 bits. I don't know where you got 2211840 bits.

Click to expand...

He got that because they miscalculated the number of bits in the device.

In Datasheet of Artyx7 XC7A100T has 270 18KB blocks

Click to expand...

wrong 18KB (kilobytes) should be 18 Kb (kilobits)

8x1024 is equal 1KB
8x1024x270 is equal 2 211 840bits

Click to expand...

This calculates the number of bits for 270 8192-bit RAMs, which isn't the same as 18Kb RAMs.

OP stop switching between byte and bits every other calculation that just makes YOU confused.

18Kb RAM bits are only fully usable if you use the parity bit, i.e. configuring the RAM as 512x36-bit, 1024x18-bit, or 2048x9-bit. As you are using only 8-bit data you will only have 2048x8-bit or 16384-bits.

16384 x 270 gives you a maximum of 4423680-bits that are usable in your application. Unless you pack data an configure the RAM as 2048x72-bits (i.e. eight 2048x9-bit RAMs). This configuration will only allow you to use a total of 264 of the RAMs or 4866048-bits.

to save image frame from camera needed 9 830 400s (1280x960x8) bit but cannot make Bram IP, can save little more than 4 915 200s (1280x960x4) but

Click to expand...

most designs use DRAM to store image data as that allows you to store many image frames. FPGA RAM is usually not used for frame buffers.

Hello, one question when we use Dual port BRAM as a interface to DDR3, A side port can be 8 bit port and B side port 128bits, and address respectively 11bits and 8bits, when FrameValid and LineValid is ON, data is available, so that time address increase to 1, and write enable is 1 when data valid . and B side has 128bits wide which connects to DDR3, how to write B side address, there only 8bits address, maximum is 256 addresses can be, write Aside based on camera's FrameValid and Line valid , but Bside can be based on what ?

and i found several tutorial where use FSM machines write and read from DDR3 by only one clock , it can be used 2 clock domains and two FSMs ?

I highly suggest you use one or the other.
The BRAM will be easy to access, and you can load random addresses for single reads.
If you try and use DDR the same way, you will get terrible performance. DDR likes doing large burst read and writes. Single word reads/writes will result in high latency between read/writes.

It is quite usual to have a BRAM for buffering data in and out of RAM.

How you address it is up to you.