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what is the difference between @posedge clk or negedge rst or posedge rest

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ajaz

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Hi All,

can anyone share me basics of clk and rst - i can't able to visualize when to use posedege and negedge.

Please suggest me Material or video. it would be great help for me.
 

Hi,

These are rather basics for digital circuits...
Thus it's explained in flip flop functions ... and eveywhere else

What's exactly the problem?
* RESET and CLOCK?
--> RESET sets (a flipflop ... a system) to a default state. CLOCK is the (synchronous) timing reference for data or other signals.

* Or EDGE?
--> a transition of a digital signal from HIGH state to LOW state or vice versa.

* Or POSEDGE and NEGEDGE?
--> pos = rising = from_LOW_to_HIGH; neg = falling = from_HIGH_to_LOW

Timing diagrams, signal flow charts, truth tables are given many million times in the internet....in almost any digital IC/circuit /device datasheet. ...video, tutorial...

Klaus
 

Go to your institution library (unless you are restricted by covid19 lockdown in your region) and get a digital design book rather than looking for material in the internet.
Reading a book is always recommended over any other material.
 

The difference between posedge and negedge reset is in the active reset level, an arbitrary design decision.

I presume you are referring to the commonly known design template for an edge triggered FF with asynchronous reset. You don't find it in the Verilog language reference manual but in RTL compiler reference manuals, e.g. for Synopsys Design Compiler. Notice that an edge sensitive event is used to describe a level sensitive (asynchronous) reset. This is somehow counter-intuitive but has been adapted as standard by all RTL compiler tools. 

Code Verilog - [expand]
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always @(posedge CLOCK or negedge reset) begin
  if !reset begin
    ... statements ...
  end
  else begin
    ... statements ...
  end
end
 

The standard cells usually support both posedge reset and negedge reset flops. I am not sure, if there is any specific reason, one would go with posedge reset vs negedge reset. Like FvM mentioned, it could be arbitrary design decision.
 

This looks as though it might be germaine...
When assembling a counter from flip-flops, you need to mind whether transitions are positive or negative going, depending on whether you want to count up or down.

Even though the devices themselves are level-sensitive, yet they look as though they yield opposite results based on direction of edge-triggering.

4-bit counters toggle FF's one up one down direc 7 sgmt displays.png

By tapping each Q output (instead of not-Q), it changes the upper circuit to a Down counter, and the lower circuit becomes an Up counter.
 

Code: 
always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
    // if negedge rstn occurs now , this case is reached.  negedge rstn
    // means rstn has just now transitioned to 0 and this case is reached when
    // rstn == 0.
    // if posedge clk occurs now while rstn is low, this case is reached
    // as well and the clk transition is ignored -- the FF is held in
    // reset.
    q <= 1'b0; // q gets 0 when rstn goes low.
  end else begin
    // it is impossible to reach this point if negedge rstn happened now.
    // likewise, it is impossible to reach this point if posedge clk
    // happened now while rstn == 0.
    // the only way to get here is for posedge clk to happen now while 
    // rstn == 1.  so this is what happens on clock edges when the
    // circuit is not reset.
    q <= d; // q gets d on rising edge clk.
  end
end

// if you want a falling edge clk sensitivity, use 'negedge clk'.
// if you want active high reset, use 'posedge rst' and 'if (rst) begin'.
//
// This is the one case where the synthesis tools make use of the
// sensitivity list to infer behavior in synthesis.  normally the sensitivity
// list is ignored in synthesis.  So don't try to get too creative with
// them.  use the above pattern and always@(*).
// or use always_ff/always_comb if you have SystemVerilog.

(also, I'm not a fan of down counters with async resets.)
 

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