Saraadib
Member level 4
Hi All,
I design a kind of switch capacitor filter which include a clock generator that create 4 non overlap clock to drive the switch for switch capacitor filter.
So,I have done simulation for 1GHZ and 1.25GHz (clock frequency).
The problem is for fclck=1GHz,schematic and RLC extraction works but For fclck=1.25GHz , schematic work but RLC extraction simulation ,PSS does not converge.
I should mention that I use PSS+PAC to simulate the filter response.
I have attached the log file for more information
Any body have idea how to solve converge problem for PSS?
Here is my log file:
I design a kind of switch capacitor filter which include a clock generator that create 4 non overlap clock to drive the switch for switch capacitor filter.
So,I have done simulation for 1GHZ and 1.25GHz (clock frequency).
The problem is for fclck=1GHz,schematic and RLC extraction works but For fclck=1.25GHz , schematic work but RLC extraction simulation ,PSS does not converge.
I should mention that I use PSS+PAC to simulate the filter response.
I have attached the log file for more information
Any body have idea how to solve converge problem for PSS?
Here is my log file:
Code dot - [expand] 1