ASIC datapath design: Back-pressure (Stall) mechanism

Hi All,

In ASIC design what are the best practice/industry standard for back-pressure (stall) mechanism.

Example -

Consider ASIC datapath with N-pipeline stages, where last stage is a FIFO which writes data into a shared memory (i.e. there are other independent blocks accessing the memory as well, and write-access to memory is not guaranteed).


Scenario 1) First (N-1) stages are all comprised of "combo logic" followed by registers to store outputs of each stage. There is no "feedback" from registers (e.g. no accumulators).

If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory ....... we would need to "freeze" all previous (N-1) stages immediately.

=> How should this be implemented ? A "output FIFO full" signal that acts as clk-gating signal to all previous (N-1) stages ? If N is large, this might be a high-fanout net and might cause synthesis setup-violations. Is there any alternative solution ? How is this done in industry ?


Scenario 2) If somewhere in the middle (say N/2 stage) is an accumulator pipeline stage, which accumulates 'M' terms before providing valid output to next stage. All remaining (N-1) stages are same as B]Scenario 1[/B].

If last stage FIFO ("output FIFO") gets full and is unable to write anymore into the shared memory for -
* Less or equal to M cycles
* Greater M cycles

=> How do we implement stall/back-pressure ? It seems that we can (and should) allow pipe-line stages before accumulator to continue working upto additional M-cycles. What about stages after accumulator. How would stall/back-pressure mechanism be implemented ?


I would be grateful for any in-depth suggestion (also I would like to know if there is any recommended book regarding this matter).

Thanks,
a1129m

Suppose say you have 6 pipeline stages and a fifo after that. When the write pointer in the fifo points to FIFO_DEPTH-6-1, you can send a signal to the source of the data to the first pipeline stage saying not to send data anymore.

@vyella1 Thanks for replying.

Let me clarify your suggestion -

Assumption:
"Scenario 1" with N=7 (7th stage being output-FIFO).

Proposal:
* Create (fifo_ptr == (FIFO_DEPTH-6-1)) signal and use this to stall Stage-1 (and let Stage-2 to 6 continue operation)
* <Unconfirmed> Most likely you are also proposing to stall subsequent stages with unique signals e.g. (fifo_ptr == (FIFO_DEPTH-6-2)) signal to stall Stage-2 etc


Issue:
* This solution is much more complicated than simply stalling ALL stages (i.e. 1 to 6) when (fifo_ptr == (FIFO_DEPTH-1)).
* The proposed solution creates "bubbles" that we will need to track, when finally output-FIFO offloads data to shared memory i.e. when operation resumes (because data coming in to various stages is no longer valid).
* From overall HW-architecture point of view, the proposed solution doesn't provides any advantages ........since these "bubbles" will negate any possible benefit we could have achieved by allowing other stages to function normally (i.e. stalling only Stage-1, not Stage-2,3,4,5,6 when "(fifo_ptr == (FIFO_DEPTH-6-1))" ).

I'm facing a problem which is lot more complicated than above two scenarios ...... I'm hoping for simple/elegant solution that I can scale up to arbitrary complexity. Let me know your thoughts.

a1129m

You can either do back pressure to all the pipeline stages, or instead send a signal from the fifo to the source(suppose say ab) of first pipeline stage saying not to send the data. From that source ab there will be a signal going to it's source not send any data. The reason I suggested FIFO_DEPTH-6-1 (assuming 6 pipeline stages) is when you send a signal to source ab, there shouldn't be any incoming data to the pipeline stages and the data in all 6 pipeline stages can be written to the FIFO. In my case I need to use this logic.