[SOLVED] Back-to-back MOSFET circuit not working

Hi,
Circuit purpose is to sense presence of a resistive load in order to enable an SMPS and LDO (the 5V input) before a mechanical switch is turned on, otherwise SMPS and LDO should be off to save Iq.

It worked correctly with only Q1 + Q2 and the difference amplifier and comparator. With Q3 +Q4 (and then adding Q5 + Q6 to isolate X node from difference amplifier when 5Vout is enabled), this circuit simulates terribly: either 5V output overrides 2.662V output or it oscillates on and off when delay RCs are used on 5Vout drive circuit, and similar failed workarounds. Adding pull-downs to common-drain connections or difference amplifier Y point/node doesn't help.

I'n guessing it may be related to lack of understanding of interplay of source and drain voltages and some naïve design error at node X?

Can an adult tell me what must be obvious that I just don't grasp, please?

You show boxes, not Mosfets. The datasheet of the FDD4141 shows Mosfets and the body diodes they have in them. Their connections are not shown as 123 like you show.

Hi,

Audioguru said:

You show boxes, not Mosfets. The datasheet of the FDD4141 shows Mosfets and the body diodes they have in them. Their connections are not shown as 123 like you show.

Click to expand...

Very witty, I don't like the yellow box Spice model, either, no idea why they didn't use a standard PMOS shape. You mean I wrote K---A backwards with the vertical FETs... My mistake.

Here is an FDD4141 description and simulation pertinent to your remark. I use it the right way round, there was no definition of Spice model pins so in 2017 I had to do an identical circuit to identify source and drain.



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Hi,

Added cleaned-up/simpified schematic of circuit. Is there any reason this circuit can't work:

With no resistor at node B, pairs 1a and 1b should be on and pair 2 should be off.
With a resistive load at node B, pairs 1a and 1b should be off and pair 2 should be on.
In simulations, it oscillates/chatters on and off before the resistive load is connected via the timed switch.
In DC value analysis, with no load there is >3.5V at node B and with any load (1G down to 1R) there is an operatiing point error message at node C1.
Pull-down resistors at each floating node don't solve the issue, and mess-up the expected 2.662V + op amp offsets (around 12mV in total at the comparator input).



Lastly, any reason images called e.g. DSC_1234 don't upload on the forum?

Thanks

"Operation point" error is a simulator rather than a circuit problem. It doesn't tell much about the circuit itself. Usually it can be bypassed when understanding simulator requirements.

The purpose of the circuit isn't quite clear, particularly why you are using power MOSFET to switch low power signals. Your description of transistor "on" condition isn't exactly correct. PMOS transistors are turned on if the gate to source voltage difference is exceeding the threshold. To achieve this for all possible circuit voltages, you need a negative gate bias source.

Hi,

Okay, great. Not familiar with TINA error workaround options except for changing iteration from 20 to 100 or time step from 10G to 1m, etc.

Good point: Using power MOSFETs as pair 2 need to pass 1.3A and for pairs 1a and 1b just because FDD4141 is what I have in Spice modes with low RDSon and VGS up to +-20V and copy-pasted back-to-backs from a charging circuit..

Purpose of circuit, silly or not, is to see whether it is possible to electronically sense (i.e. not via a mechanical switch or a barrel jack) when an external load is connected to a circuit in order to wake up/enable a SEPIC and an LDO. Partly to see if it's possible to implement and partly with idea of offboard load not seeing start-up transients of SMPS and LDO. An unnecessary circuit add-on, maybe, but the idea intrigues me - sensing a load being connected due to a change in a resistance value when a parallel resistive load is added and therefore a change in a sensed voltage level.

Working through a circuit design on a 12V supply with estimated ~1W Iq . When circuit is designed/complete I want to go down to 5V housekeeping supply and turn off any sub-circuits when not in use that can be. In an analog heaven of hardware as I try to learn a bit more and happy there...

Thanks, had the impression of not understanding FET operation too well beyond PMOS gate to Vdd is on and to Vss is off and viceversa for NMOS.

Had another fight with the circuit this afternoon with no success again. Maybe an app note that uses common source rather than common drain back-to-back PMOS does so for a good reason.

Thanks for your help.

common drain won't work for fairly obvious reasons - gate drive signal is always w.r.t. source ...

As long as the gate voltage is referenced to the circuit common, common source isn't necessarily better.

But you need to care for sufficient gate-source voltage in any case. The advantage of common source is that substrate diodes bias the common source node to the higher of both drain voltages. With common drain, both source nodes must be biased independently, which is apparently not achieved in the discussed circuit.

:thumbsup:

Just super, chaps. Thanks so much for your help and great explanations. I understand. Thank you.

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most common AC mosfet switches are source to source ( see internet ) - I have never seen common drain before. Common source allows single gate drive.