# Nonlinear capacitor in Cadence Virtuoso/spectre?

1. ## Nonlinear capacitor in Cadence Virtuoso/spectre?

Hi,

Fairly trivial question: What is the proper way to model a nonlinear capacitor in Virtuoso?

In LTSpice, I can just use an expression like this:

Code:
`Q=1e-6*x+a*1e-6*0.5*tanh(2*x)`
In Cadence, I tried the following:

Code:
`C1 (vout 0) capacitor c=1e-6*(1+0.5*v(vout,0))`
However, first I would need to manually add the node name "vout" into the expression ... which means if I change the name of the output node in Cadence I need to change it in the object properties as well.
Second, the variable "vout" always lands as a variable in my ADE L window when I start simulation.
Hence I am not sure this is the right way to do it ...

2. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Originally Posted by exp
in Virtuoso?
What do you want to mean ?

Originally Posted by exp
What do you want to mean ?

Use correct terminology.
Understand things correctly.

If you use Cadence Spectre, use spectre’s primitive “bsource”.
See “spectre -h bsource”.

Or use Verilog-A.

3. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Thank you, got it working now. In the netlist it looks as you wrote (just with capacitor instead of bsource) ... in ADE L I instantiate a capacitor and write the expression C*(1+b1*v(vout,0)) for capacitor value.

However, when I start simulation in ADE L it treats "vout" as variable that is filled into ADE L and gives a warning. Simulation still works (I checked the results) but it's pretty annoying and confusing:

Is there a way to avoid this?

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4. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

You can not understand Cadence Spectre at all.

Surely see and undestand bsource.

5. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

I understand bsource and spectre ... it is working.

6. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Originally Posted by exp
I understand bsource and spectre ... it is working.
Or use netlist fragment include.

You can never utilize full ability of Cadence Spectre as far as you rely on Cadence ADE.

I will describe model as three or four terminal device by Verilog-A.

module aho_cap(pos, neg, ctrl)

or

module aho_cap(pos, neg, ctrl, ref)

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7. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Are you sure that a properly parameterized, native
diode or MOS capacitor model (with or without a
companion "bulk cap" for the non-variable part)
couldn't be fitted up "well enough"? Both are widely
used as variable (nonlinear) capacitors in RFICs.

8. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Assign an initial value for "vout" in variables list in ADE.Either enter it manually or automatically import from schematic.Otherwise it won't work as wanted..

9. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Originally Posted by BigBoss
Assign an initial value for "vout" in variables list in ADE.Either enter it manually or automatically import from schematic.Otherwise it won't work as wanted..
”vout” is a node name.

10. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Originally Posted by pancho_hideboo
”vout” is a node name.
We don't know it. This statement is based on assumption that our dear friend done everything properly.

So, dear exp, show us a netlist and spectre log.
It might be a bug in ADE L (as I know it is deprecated tool), however it might be not.

11. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

Originally Posted by dick_freebird
Are you sure that a properly parameterized, native
diode or MOS capacitor model (with or without a
companion "bulk cap" for the non-variable part)
couldn't be fitted up "well enough"? Both are widely
used as variable (nonlinear) capacitors in RFICs.
It will, eventually. But right now I am working with behavioral models and first need to match the behavior of my circuit with hand calculations.
So yes, right now I need a nonlinear cap where I can set the nonlinear C(V) curve precicely

Originally Posted by Dominik Przyborowski
We don't know it. This statement is based on assumption that our dear friend done everything properly.

So, dear exp, show us a netlist and spectre log.
It might be a bug in ADE L (as I know it is deprecated tool), however it might be not.
Yes, indeed it is a node name. This the net list:

Code:
```// Generated for: spectre
// Generated on: Apr 14 04:45:04 2020
// Design library name: test
// Design cell name: test_nonlinear_cap
// Design view name: schematic
simulator lang=spectre
global 0
parameters _EXPR_2=9.765625e-10 Pin=-23 vout fin=1M \
b1=1 C=1n R=1k

// Library name: test
// Cell name: test_nonlinear_cap
// View name: schematic
C1 (vout 0) capacitor c=C*(1+b1*v(vout,0))
PORT0 (vout 0) port r=R type=sine freq=fin dbm=Pin-6 fundname="fin"
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
pss  pss  fund=10k  harms=49  errpreset=conservative
+    annotate=status  strobeperiod=_EXPR_2
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub```
As I said, the simulation (in spectre) itself works, I think it is an ADE L issue. It does not realize that it's a nodename and wants to import the variable into ADE L.

Creating a separate netlist and important sounds like an option, yes, although not ideal.

Originally Posted by BigBoss
Assign an initial value for "vout" in variables list in ADE.Either enter it manually or automatically import from schematic.Otherwise it won't work as wanted..
I did not expect this to work because I assume "C1 (vout 0) capacitor c=C*(1+b1*v(vout,0))" would be replaced with "C1 (vout 0) capacitor c=C*(1+b1*v(0,0))" which is the same as "C1 (vout 0) capacitor c=C".
However, I tried just setting vout to some number in ADE L (e.g. 0) and it seems it still works:

Code:
```// Generated for: spectre
// Generated on: Apr 14 05:00:47 2020
// Design library name: test
// Design cell name: test_nonlinear_cap
// Design view name: schematic
simulator lang=spectre
global 0
parameters _EXPR_2=9.765625e-10 Pin=-23 vout=0 fin=1M \
b1=1 C=1n R=1k

// Library name: test
// Cell name: test_nonlinear_cap
// View name: schematic
C1 (vout 0) capacitor c=C*(1+b1*v(vout,0))
PORT0 (vout 0) port r=R type=sine freq=fin dbm=Pin-6 fundname="fin"
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
pss  pss  fund=10k  harms=49  errpreset=conservative
+    annotate=status  strobeperiod=_EXPR_2
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub```
This solution is not optimal either (since I have now the bogus "vout" variable in ADE L) but at least the error message is gone.

12. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

It seems that in some cases, netlister treat formula as nested one, and force node name to be a variable to set initial conditions.

To work around I would try to check following hypothesis/steps:
1. replace port with a voltage source with defined dc
2. replace capacitor with charge element (bsource with formula for charge, when dq=c(v)dv) - will need to calculate indefinite integral for charge
3. define at least initial phase for port signal (maybe explicitly other parameters)
4. define initial conditions for capacitor (analogLib cap has such parameter)

13. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

While veriloga has ability to do maths on -results- during
execution, I don't believe SPICEs or Spectre will do so.

C1 (vout 0) capacitor c=C*(1+b1*v(vout,0))

says to me that (a) function v() would be looked for and
want a declaration, as a netlist argument, (b) the vout
argument to the v() function also wants definition as it
is in a "value" field, not a "connectivity" field of the
netlist line.

Have you tried making a veriloga capacitor model?

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14. ## Re: Nonlinear capacitor in Cadence Virtuoso/spectre?

In Cadence Spectre, resistor, capacitor and inductor which have behavioral expression are actually Spectre's primitive "bsource".
They are alises for Spectre's primitive "bsource".

Cadence Spectre did not have an abilty for behavioral expression in resistor, capacitor and inductor.
On the other hand, Synopsys HSPICE have them from first.

Many device model files are provides as HSPICE syntax.
Spectre's primitive "bsource" were introduced for comatibilty with HSPICE netlist, since HSPICE is a golden standard simulator.
So Spectre's primitive "bsource" are not oriented as instances in schematic.

Use netlist.
Or use Verilog-A module instead of bsource.

"bsource" is actually expressed by Verilog-A in Cadence Spectre.

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