I am using Design Compiler to insert a scan chain in a design, but when simulating after insertion the Scan Data Out is inverted with respect to Scan Data In.

I can see the scan data being inverted at several points throughout the scan path, however it always ends up being inverted for the output.

The commands I am using for scan insertion is below. I have tried the same steps on a different design and the scan path is correct.

I have tried:
  • Using the hookup_sense option in set_dft_signal (no effect either way)
  • Setting test_disable_find_best_scan_out (true and false)
  • Performing the same steps with another design (works correctly)

I can't find anything in the DFT Compiler user guide relating to this other than the items above. It does say it will choose to take Q or QN as a scan data output depending on fanout, but not why the final output might be inverted.

Any help would be greatly appreciated.


    set_dft_drc_configuration -internal_pins enable 

    set_dft_signal -view existing_dft -type ScanClock   -hookup_pin PAD_Clock/C  -timing {5 15}
    set_dft_signal -view existing_dft -type Reset       -hookup_pin SYNC_DFC1_2/Q -active_state 0
    set_dft_signal -view spec         -type ScanEnable  -hookup_pin PAD_Test/C  -port Test   -active_state 1
    set_dft_signal -view existing_dft -type TestMode    -hookup_pin PAD_Test/C  -port Test   -active_state 1
    set_dft_signal -view spec         -type ScanDataIn  -hookup_pin PAD_SDI/C   -port SDI 
    set_dft_signal -view spec         -type ScanDataOut -hookup_pin PAD_SDO/I   -port SDO 



    set_scan_configuration -chain_count 1