Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
* IRef pulls down the voltage of node N
* Left side Mosfet tries to pull this node up ... with it's R_DS.
Now let's assume R_DS is constant (which isn't the case for steady state... but just for the very first moment)
Then twice IRef would cause twice the voltage drop across DS, thus decreasing the voltage on node N.
But the same time V_GS increases ... this makes that R_DS becomes lower, reducing the voltage drop.....but this can't compensate the voltage drop by 100% because it still needs to make R_DS lower (than at the beginning) which means ...it needs a higher V_GS.
And higher V_GS means lower voltage at node N.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
