Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reset Value using a parameter

Status
Not open for further replies.

stanford

Full Member level 2
Joined
Feb 16, 2014
Messages
132
Helped
4
Reputation
8
Reaction score
6
Trophy points
1,298
Activity points
2,223
Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data.

Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <= WIDTH'd (RESET_VALUE);
  else
    ....

How do I make this work syntax wise? Is it even possible?

Thanks!
 

Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data.

Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <= WIDTH'd (RESET_VALUE);
  else
    ....

How do I make this work syntax wise? Is it even possible?

Thanks!

this is one of the few things I really like about system verilog, this problem went away completely.

in verilog, I believe you can use the concatenation operator {} to bypass this. you can use ifdefs too, but they are not as nice as parameters
 

I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?
 
Last edited:

I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?

I don't have a simulator to test right now, but I am pretty sure this is valid svlog code:

Code:
logic [999:0] myvar;

always (*) begin
    myvar = 'd0;
end
 

There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly.
Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <=RESET_VALUE;
  else
    ....
 

There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly.
Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <=RESET_VALUE;
  else
    ....

are you sure about verilog? integer constants are treated as 32 bit integers, as far as I remember. so in your example, if data has more than 32 elements, only some would be resetable.
 

I'm sure. Verilog (and thus SystemVerilos) implicitly extends or truncates the width of the RHS of a procedural assignment to match the LHS.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top