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    Conflict between two axi masters.

    Hi,

    This is about the axi3 interconnect. Here , In my SoC there is a axi3 interconnect with two masters A and B. where A is a CDMA and B is a processor .
    And only one axi slave is connected to this interconnect.

    The issue is, when the master B requests a data from the slave. then there is no problem the axi3 interconnect taking the data from the slave and directing the data to the Master B only.

    but when the Master A initially performs some operation and completes it successfully, now if master B requests any data from the slave then the axi3 reading the data from the slave and offering it to Master A but not for Master B. It's like the master A (CDMA still holding the bus). how to avoid this situation. Here the CDMA(master A) is custom written , and axi3 and others are dw components.

    Any idea ?

    regards,
    hcu

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    Re: Conflict between two axi masters.

    Are you expecting that the slave will give data to two masters at the same time? This cannot happen.
    The slave is connected via only 1 set of AXI bus.
    Until and unless a transaction is completely over between one master and the slave, the other master will just be waiting for the *READY signal from the slave.

    Does that answer your question.
    FPGA enthusiast!



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    Re: Conflict between two axi masters.

    No. I think its deviated.

    The processor(Master B) requesting a data from the slave(a memory buffer with axi slv interface logic) . the slave giving the data to the AXI3 slave port (i can see that data is presented back to interconnect slave port) . but on the other side (i mean at master ports) that data appearing at the Master A port but not at Master B port.



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    Re: Conflict between two axi masters.

    I cannot comment more.

    You need to check individual axi channel transactions and verify that the channel handshakes are happening properly. Maybe you can find a problem there.
    Check also the signals traveling up and down the axi interconnect.
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    Re: Conflict between two axi masters.

    Do you write the slave yourself? The way you described your problem, it looks like both the CDMA and the interconnect are not written by you.
    Assuming you are using AXI-MM, it recognizes each master by assigning them with a unique ID. I guess either both your master use the same ID (e.g. arid for AXI read); or your slave keeps returning the same ID (e.g. rid); or your AXI interconnect is modifying the ID itself.



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    Re: Conflict between two axi masters.

    Quote Originally Posted by dpaul View Post
    I cannot comment more.

    You need to check individual axi channel transactions and verify that the channel handshakes are happening properly. Maybe you can find a problem there.
    Check also the signals traveling up and down the axi interconnect.

    Initially I found that the master (processor) not getting its requested RVALID ,RDATA, RLAST from the slave. I thought of problem with the slave which may be not responding.

    But, After adding all the signals to the wave window then only i figured out that the RVALID , RLAST and RDATA nicely going to Master (cdma) but not to processor.

    here the requested one is processor but the axi-interconnect directing the traffic from the slave to cdma master.


    Anyhow thank you. I'll double check by adding all limbs of AXI interconnect into wave window and observe transactions.



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