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How to parallel process foreach_in_collection in ICC?

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pradeep5344

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Hello,

Can someone help me with code snippet on how to parallel process foreach_in_collection loop?

I have huge list of collections nets/pins/cells for which i want to loop through ?

Going one after another in a serial manner is taking hours to run a scripts. is there a way i can have my big list to be split into parts and have loops execute in parallel ?

Thanks in Advance, please do let me know if there is a way to handle this better.

-Regards
Pradeep
 

Consider breaking it up at least by major-loop iterations
and farm it out to N processes each with a slightly
differentiated circuit file. Then you just have to combine
the data.

If you're clever you might make a script that builds and
launches such a run-set from a collection of header, body,
footer files and a little bit of "variation goes here" code.
 

Thanks for reply.

Do you have any example code for this?

Below is what i am trying to do which is on a large collection. which is taking 1 hour for 100k pins.
HTML:
###########################################################################
#proc to trace back from input to driver through buffers/inverters
proc trace_back_bufinv { pin } {
    set i 0;
    set not_buf false;
    set not_inv false;
    while {1} {
      set out [filter_collection [all_connected [get_flat_nets -of $pin] -leaf] "direction==out"]
      if {[sizeof_collection $out] == 0} { set out [filter_collection [all_connected [get_flat_nets -of $pin] -leaf] "object_class==port"]}
      set cc [get_flat_cells -of $out -quiet]
      if {[sizeof_collection $cc] == 0 } { set cc [get_attribute $out design] }
      if {[get_object_name $cc] == [get_attribute [get_designs] top_module_name]} { 
         set ref [get_attr [get_designs] top_module_name] } else {  set ref [get_attr $cc ref_name] }
      if {[regexp {_buf} $ref]} { set not_buf false; } else { set not_buf true}
      if {[regexp {_inv} $ref]} { set not_inv false; } else { set not_inv true}
      set pin [get_flat_pins -of $cc -filter "direction==in"]
      incr i;
      if {$not_inv && $not_buf} { return [get_object_name $out]; break }
    }
}

#proc to trace front from output to loads through buffers/inverters
proc trace_front_bufinv { pin } {
    redirect -variable testfront {report_buffer_trees -from $pin -hierarchy}
    set sink {}
    foreach line [split $testfront "\n"] {
        if {[regexp -nocase {Load } $line]} { lappend sink [lindex $line end-1]  }  
    }
    return $sink;
}
#----------------------------------------------------------------------------------------------------------------------------------
       set mod_cells               [get_flat_cells -of ${module_cell} ]
       set mod_cells_pins          [get_flat_pins -of  ${mod_cells}      -filter "port_type==signal && name!=ret && name!=nret"]
 
    foreach_in_collection mcc $mod_cells_pins {
            incr i;
            set direction [get_attribute $mcc direction]
            if {$direction=="in"} {
              set drivers  [prd_trace_back_bufinv $mcc]
              set drivers  [get_flat_pins $drivers -quiet]
              set drivers  [add_to_collection -unique $drivers [get_ports $drivers -quiet]]
              set loads    $mcc
            } else {
              set drivers  $mcc
              set loads    [prd_trace_front_bufinv $mcc]
              set loads    [get_flat_pins $loads -quiet]
              set loads    [add_to_collection -unique $loads [get_ports $loads -quiet]]
            }
    }

###########################################################################
 

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