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  1. #21
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    Dominik Przyborowski's Avatar
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    Re: Cascoding the two stage folded class AB ampliifer

    1. All guys has the same dimensions (absolute, not ratio)
    2. ×3 stacked guys below diode are triodes with total V_DS equal to VDS_SAT (in ideal case there is a voltage source)
    3. Considering biasing circuit is for double cascode CS working in 1st stage of opamp from thread beginning

    Short story - this is replica to ensure the same V_DS for each biasing diode as has biased by them transistors in amplifier. It makes circuit insensitive to current mismatch caused by non-flat output characteristic (finite drain impedance, channel modulation, DIBL and so on).

    Longer story: voltage at drain of upper cascode is determined by output FET gate voltage which is following diode connected FET from Monticelli bias (MN8). So, the VDS of this guy is upper limited. It means, that for the same current his VGS has to be higher then VGS of ordinary diode. It makes VDS conditions for middle guy (cascode) stricter and story repeats. In worst case situation is the most important guy - bottom FET - a current source which is squeezed by cascode and upper cascode together. So, every branch in bias circuit (ok, every - 1) limits diode VDS by VGS of lower guy. So, in middle branch cascode diode is covering upper cascode, while current source diode is covering both cascodes.

    The triodes provides minimum and constant (more-or-less) VDS for transistors placed below guy which is biased from particular branch.

    Sources… Another tricky question. Basically, it is nothing more then logically expanded single cascode bias. Whole concept was invented by Sooch more then 30 years ago. Initially, it was single branch with two diodes with shifters stacked together. It can be easily split to two branches (then it needs single diode for headroom and works in low supply environments) as you have been able to see in many examples (i think in 4th edition of Gray, Hurst, Meyer book it was described).
    The whole concept of level shifting is also nothing more than circuit known as gate follower - should be described in every book behind common source, drain or gate guys. Degenerated current sources uses the same concept. So, if you face problems to find it in CMOS books, take some real electronics - mean BJT.

    Lastly, if you are not satisfied with lack of recipe for VDS of current source (or generally this triodes level shifters), you can try to calculate it by yourself.
    By applying any compact model formula binding channel charge (or current) with pinch-off voltage like:
    Vp/n - V_S = Vt·[sqrt(1+4·i)-2 + ln(sqrt(1+4·i)-1)],
    where Vp is pinchoff voltage (for simplicity we can say it is 0 if gate voltage is equal to infamous threshold voltage), V_S is source voltage, Vt=kT/q is thermal voltage and i is unit-less normalized current (precisely forward current, details you can find it in literature about compact modelling) equal to ratio of actual drain current and transistor "specific current" defined as Ispec=2·n·Vt²·K·W/L, where K≈µeff·Cox is current gain factor.

    The last formula giving simple relation between Ispec for various W/L ratios - if we defined technology current as Ispec=Itech·W/L, it gives Itech the same for all transistor of the same flavor in process and makes makes i scalable with W/L ratio (or number of fets in stack or parallel if they are the same and bias current is the same, too).

    So, if we suppose that for Ibias and W/L, we have i=10 and Vp=Vgs-Vth, and Vth is constant for all guys and set to 0.5V, then single diode has Vgs≈0.7V
    Knowing that Itech is the same for all dimensions, and that 4 transistors in stack can be modeled as single transistor with Leff=4L, so such guy has i 4× higher (this case 40) and thus VG≈0.92V. If we subtract VGS of unit diode from diode made by 4 in stack we get VDS≈0.22V. The same we can apply to another branch, or by assuming desired VDS for triode shifter, we can estimate number of guys in stack.

    I hope it will not complicate your look on current mirrors.
    If you start to looking for some compact modeling literature, you can find several approaches - some are more "physical" some other more "mathematical" - it means that assumptions or basic points might differ a bit. Also, some equations might not be solved accurately, rather approximated by functions with more friendly properties (like approximation with poly-logarithms instead of direct Lambert W solution, etc.)
    However, important is to not drown and die in the complicated math, but rather use common sense and engineering way of thinking, that every curve is a straight line.

    Good luck with design.

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  2. #22
    Advanced Member level 4
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    Jan 2012
    44 / 44

    Re: Cascoding the two stage folded class AB ampliifer

    Dear Mentor Dominik

    I am very grateful to your amazing explanation, I am studying it befoe I comment any thing

    Thank you very much once again

    Best Regards

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