# matching network design question

1. ## matching network design question

Hello, i have built a matching network of 13dB gain and NF as shown bellow step by step.(including all the plots and matlab )

its just not working at all,i am doing it exacly by the thoery

taking a point inside the circle-> converting its gamma to Z_source->converting gamma_s into gamma_L with the formulla bellow as shown in the matlab->converting the gamma_L into Z_L-> building the matching network for conjugate of Z_L and Z_c.Its just not working.

where did i got wrong?

Thanks.

```Code dot - [expand]1
2
3
4
5
6
7
8
z_s=gamma2z(gamma_s,50);
s11=0.99875-0.03202*i
s12=721.33*10^(-6)+8.622*10^(-3)*i
s21=-188.37*10^(-3)+30.611*10^(-3)*i
s22=875.51*10^(-3)-100.72*10^(-3)*i
gamma_L=conj((s22+(s12*s21*gamma_s)/(1-s11*gamma_s)))
z_L=gamma2z(gamma_L,50)```

2. ## Re: matching network design question

Did you hear about this new stuff, so called operating point? Browse for it. Your NMOS is technically closed, the PMOS is rather a resistor than transistor.

•

3. ## Re: matching network design question

Hello,Yes you are correct the matching network tottaly ruins the biasing point(which was in saturation before addind the matching networks as show bellow)
What should i do?
We could add some biasing VDC source separatly to the port (with a DC BLOCK capacitor) but the added capacitance will distort the matching network.
So the question comes to what capacitor should i add in series to VDC so it will not distort my matching network?
or is there some other method?

4. ## Re: matching network design question

I don't know or understand how do you imagine the modification. Here is what I would do:
1. delete the PMOS and move L1 between NMOS drain and VDD
2. create an NMOS bias circuit: series IDC source + diode connected NMOS device
3. connect the diode connected device's gate/drain voltage to your NMOS (M0) gate through a big value resistor or RF choke

•

5. ## Re: matching network design question

Hello, i will try to follow your method.
I have mannaged to get the following result(shown bellow) by adding a DC block of less then 1ohm in 10G and large impedance at 10G
but as you see those DC blocks and RF CHOKE come in direct contact (signed as 1 2 3 in the photo)with the matching network.
assuming our DC is fine and we are in saturation,how do we make sure that thos DC blocks and RF chokes will not ruin thematching network functionality?
Thanks.

6. ## Re: matching network design question

Some definite amount of ohmic resistance ought to be ahead of your filter. Looking closely, that appears to be a resistor just above the waveform generator at left. Is that your intention? Does the simulator understand that is 50 ohms input resistance?

Another thing to try is to put a low-ohm resistor inline with inductors (and perhaps also capacitors ). You have LC loops which lack any resistance. It's able to resonate (or ring) endlessly, once it's instigated. With ideal components, the simulator believes it has unrealistically high Q. The result is unrealistic frequency response.

7. ## Re: matching network design question

Hello BradtheRad, Its not an ohmic resistor , its just a part of a symbol that designates a PORT in cadence virtuoso.
"Looking closely, that appears to be a resistor just above the waveform generator at left."

- - - Updated - - -

Hello frankrose,still this RF choke will come in contact with the matching network(and we need to add a DC block too)
How i will make sure they will not ruing the matching properties of the network in AC?
Thanks.

Originally Posted by frankrose
I don't know or understand how do you imagine the modification. Here is what I would do:
1. delete the PMOS and move L1 between NMOS drain and VDD
2. create an NMOS bias circuit: series IDC source + diode connected NMOS device
3. connect the diode connected device's gate/drain voltage to your NMOS (M0) gate through a big value resistor or RF choke

8. ## Re: matching network design question

If the coupling elements are big enough the matching shouln't be affected too much. Use big choke and big coupling capacitor.

•

9. ## Re: matching network design question

I came to a conclution that first we put a BIASING DC BLOCK and RF choke with only the ports and then we build matching network to the NMOS+dc block+rf choke system.
i will update tommorow

10. ## Re: matching network design question

Hello, i am trying a new method of using Z-param formulas shown bellow,
What is the zd pointed in the red arrow in cadence virtuoso ,is it Zin ot Zout?

Given that Zd is Zin How do i get the Zout in that point of the circle bellow?
Thanks.

--[[ ]]--