# How to estimate power consumption at the IP design level?

1. ## How to estimate power consumption at the IP design level?

description:
In the IP design stage, sometimes there is no actual foundry-library to test IP performance, so will use similar foundry-library (or even any foundry-library) for testing.
IP test points are: highest frequency, area, power consumption.
As for area, we can use '2-input-NAND' as the unit area, and calculate the gate-count for the area estimate.
problem:
As for the power consumption, is there any quantity as the unit for power consumption, and thus there is a quantity for power consumption estimating?

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2. ## Re: How to estimate power consumption at the IP design level?

RTL level: Using tools, such as spyglass power, joulus
Gate level: Using tools, PTPX

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3. ## Re: How to estimate power consumption at the IP design level?

I don't understand the question. The unit utilised for power is W, there is no need for a proxy for power.

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4. ## Re: How to estimate power consumption at the IP design level?

If you know roughly how frequently FFs and gates toggle for a particular design, you can multiply that factor by the number of gates times the power consumption for the average gate, for a very coarse estimate. But it's very easy to be orders of magnitude out.

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5. ## Re: How to estimate power consumption at the IP design level?

Thanks a lot. gates toggle can be as a quantity for power coarse calculate.

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'W' is an absolutely unit. I want to find a relative unit.

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