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    How to mitigate large area ground current loops in large arrays of paralleled SMPS's?

    Hi
    We are doing a 12kW power supply by paralleling over 40 DCDC modules. This question is not specifically about the modules. It is rather about the nature of “circulating currents” in such large systems, and how they can be mitigated.

    The power supply will be made of ten “blocks” in parallel. The blocks are shown in the attached.

    Obviously in such a physically large system, there will be some distance between the DCDC modules at either end of the array. Therefore inevitably, we will have large area ground current loops. This is practically unavoidable.

    As you know, a current loop, (especially one enclosing such a large area) is unfortunately a very nice “receiving antenna” for noise. So we will end up with large amounts of noise getting coupled into our circuit, and it is highly likely that the power modules will be swamped with noise and will malfunction.

    Do you agree with us that our best way to mitigate this noise will be to place “ferrite beads” in all of the current loops, such that any circulating current in any loop….will “see” at least one of the ferrite beads?

    BTW, I am absolutely certain we won’t be able to get help from the DCDC module vendor since….
    1…Our sales volumes are obviously low
    2….We are too insignificant an organisation.
    Last edited by treez; 26th March 2020 at 16:30.

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  2. #2
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    Re: How to mitigate large area ground current loops in large arrays of paralleled SMP

    "Large" is a relative term. Compared to the total power I would think noise relatively unimportant and the relatively sluggish response of the power supplies would work like an LPF.

    I would think, and I have never worked on PSU systems bigger than about 3.25KW (six 6V 90A DC supplies) so forgive my inexperience, that standard star ground and star output topology would work as well as any other.

    Ferrite beads (actually quite large rings for cables that size) are best suited to common mode rejection and that implies at least two conductors pass through them. Just adding single rings will do nothing but increase the cable inductance which could do more harm than good.

    Brian.
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    Re: How to mitigate large area ground current loops in large arrays of paralleled SMP

    Thanks, ...someone who says they have worked with these modules and systems before has assured us that our biggest problem will be "circulating currents".
    They wouldnt elaborate on exactly what they meant.

    We also wonder that if we have a common mode choke right at the output of each module, then that will make it very tricky for a ground loop current to flow?
    And the common mode choke wont look like an inductor to diff mode currents.
    Last edited by treez; 26th March 2020 at 17:37.



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    Re: How to mitigate large area ground current loops in large arrays of paralleled SMP

    "circulating currents" doesn't really tell you anything, all currents 'circulate' to be able to do anything useful. If they mean ground loops, that is something you can design out by ensuring the ground current from one PSU cannot influence the ground point potential of others. As stated before, the best way to do that is to designate a single point as 'real ground' then individually return all PSU current to that point, in other words a star topology.

    Forgive me for being wary of the choke/Ferrite ideas, they have their places of course but I'm not sure this is one of them. If you do try a common mode choke, given the high current and therefore thick wires, I would try a large Ferrite ring with two windings arranged to cancel magnetic fields rather than the more conventional wiring where they just pass through the hole side by side.

    Brian.
    PLEASE - no friends requests or private emails, I simply don't have time to reply to them all.
    It's better to share your questions and answers on Edaboard so we can all benefit from each others experiences.


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