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    Error :Syntax error near "module"

    Hello, hope everything goes well, and covid19 will stop soon..

    I am very new in Verilog, use xilinx vivado 19., want to add ddr3. what a problem cannot understand.. clock wizard and mem modules done normally step by step as in instruction..code i got from https://numato.com/kb/simple-ddr3-in...-xilinx-mig-7/



    what happen why not work ?

    Code:
    module neso_ddr3(
    
     input clk_in,
    // DDR3 Physical Interface Signals
     //Inouts
     inout  [15:0] ddr3_dq,
     inout  [1:0]  ddr3_dqs_n,
     inout  [1:0]  ddr3_dqs_p,
     // Outputs
     output [13:0] ddr3_addr,
     output [2:0]  ddr3_ba,
     output ddr3_ras_n,
     output ddr3_cas_n,
     output ddr3_we_n,
     output ddr3_reset_n,
     output [0:0] ddr3_ck_p,
     output [0:0] ddr3_ck_n,
     output [0:0] ddr3_cke,
     output [0:0] ddr3_cs_n,
     output [1:0] ddr3_dm,
     output [0:0] ddr3_odt,
    
    // LEDs to signal pass/fail
     output reg  led_pass,
     output reg  led_fail,
     output wire led_calib
     );
    
     wire calib_done;
    
     reg  [27:0] app_addr = 0;
     reg  [2:0]  app_cmd = 0;
     reg  app_en;
     wire app_rdy;
    
     reg  [127:0] app_wdf_data;
     wire app_wdf_end = 1;
     reg  app_wdf_wren;
     wire app_wdf_rdy;
    
     wire [127:0]app_rd_data;
     wire [15:0] app_wdf_mask = 0;
     wire app_rd_data_end;
     wire app_rd_data_valid;
    
     wire app_sr_req = 0;
     wire app_ref_req = 0;
     wire app_zq_req = 0;
     wire app_sr_active;
     wire app_ref_ack;
     wire app_zq_ack;
    
     wire ui_clk;
     wire ui_clk_sync_rst;
    
     wire sys_clk_i;
    
     reg [127:0] data_to_write = {32'hcafebabe, 32'h12345678,
                                  32'hAA55AA55, 32'h55AA55AA};
     reg [127:0] data_read_from_memory = 128'd0;
    
     // Power-on-reset generator circuit.
     // Asserts resetn for 1023 cycles, then deasserts
     // `resetn` is Active low reset
     reg [9:0] por_counter = 1023;
     always @ (posedge clk_in) begin
       if (por_counter) begin
         por_counter <= por_counter - 1 ;
       end
     end
    
     wire resetn = (por_counter == 0);
    
     // Clock Wizard
     // DDR3 core requires 200MHz input clock
     // We generate this clock using Xilinx Clocking Wizard IP Core
    
       clk_wiz_0 inst
      (
      .clk_in1(clk_in),
      .clk_out1(sys_clk_i)
      );
    
    // Instatiation of MIG core named `mem`
     mem mem (
       // DDR3 Physical interface ports
       .ddr3_addr   (ddr3_addr),
       .ddr3_ba     (ddr3_ba),
       .ddr3_cas_n  (ddr3_cas_n),
       .ddr3_ck_n   (ddr3_ck_n),
       .ddr3_ck_p   (ddr3_ck_p),
       .ddr3_cke    (ddr3_cke),
       .ddr3_ras_n  (ddr3_ras_n),
       .ddr3_reset_n(ddr3_reset_n),
       .ddr3_we_n   (ddr3_we_n),
       .ddr3_dq     (ddr3_dq),
       .ddr3_dqs_n  (ddr3_dqs_n),
       .ddr3_dqs_p  (ddr3_dqs_p),
       .ddr3_cs_n   (ddr3_cs_n),
       .ddr3_dm     (ddr3_dm),
       .ddr3_odt    (ddr3_odt),
    
       .init_calib_complete (calib_done),
    
       // User interface ports
       .app_addr    (app_addr),
       .app_cmd     (app_cmd),
       .app_en      (app_en),
       .app_wdf_data(app_wdf_data),
       .app_wdf_end (app_wdf_end),
       .app_wdf_wren(app_wdf_wren),
       .app_rd_data (app_rd_data),
       .app_rd_data_end (app_rd_data_end),
       .app_rd_data_valid (app_rd_data_valid),
       .app_rdy     (app_rdy),
       .app_wdf_rdy (app_wdf_rdy),
       .app_sr_req  (app_sr_req),
       .app_ref_req (app_ref_req),
       .app_zq_req  (app_zq_req),
       .app_sr_active(app_sr_active),
       .app_ref_ack (app_ref_ack),
       .app_zq_ack  (app_zq_ack),
       .ui_clk      (ui_clk),
       .ui_clk_sync_rst (ui_clk_sync_rst),
       .app_wdf_mask(app_wdf_mask),
       // Clock and Reset input ports
       .sys_clk_i (sys_clk_i),
       .sys_rst (resetn)
       );
    
     localparam IDLE = 3'd0;
     localparam WRITE = 3'd1;
     localparam WRITE_DONE = 3'd2;
     localparam READ = 3'd3;
     localparam READ_DONE = 3'd4;
     localparam PARK = 3'd5;
     reg [2:0] state = IDLE;
    
     localparam CMD_WRITE = 3'b000;
     localparam CMD_READ = 3'b001;
    
     assign led_calib = calib_done;
    
    always @ (posedge ui_clk) begin
      if (ui_clk_sync_rst) begin
        state <= IDLE;
        app_en <= 0;
        app_wdf_wren <= 0;
      end else begin
        case (state)
          IDLE: begin
            if (calib_done) begin
              state <= WRITE;
            end
          end
    
          WRITE: begin
            if (app_rdy & app_wdf_rdy) begin
              state <= WRITE_DONE;
              app_en <= 1;
              app_wdf_wren <= 1;
              app_addr <= 0;
              app_cmd <= CMD_WRITE;
              app_wdf_data <= data_to_write;
            end
          end
    
          WRITE_DONE: begin
            if (app_rdy & app_en) begin
              app_en <= 0;
            end
    
            if (app_wdf_rdy & app_wdf_wren) begin
              app_wdf_wren <= 0;
            end
    
            if (~app_en & ~app_wdf_wren) begin
              state <= READ;
            end
          end
    
          READ: begin
            if (app_rdy) begin
              app_en <= 1;
              app_addr <= 0;
              app_cmd <= CMD_READ;
              state <= READ_DONE;
            end
          end
    
          READ_DONE: begin
            if (app_rdy & app_en) begin
              app_en <= 0;
            end
    
            if (app_rd_data_valid) begin
              data_read_from_memory <= app_rd_data;
              state <= PARK;
            end
          end
    
          PARK: begin
            if (data_to_write == data_read_from_memory) begin
              led_pass <= 1;
            end else if (data_to_write != data_read_from_memory) begin
              led_fail <= 1;
            end
          end
    
          default: state <= IDLE;
       endcase
     end
    end
    
    endmodule // top

  2. #2
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    Re: Error :Syntax error near "module"

    Just inspecting the posted code I don't see anything wrong with the module, specifically nothing wrong with the module declaration.

    Are you sure you compiled the posted version of code?
    Is the title the actual message produced from the compilation?



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  3. #3
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    Re: Error :Syntax error near "module"

    I just try to compile, and it gave me ERROR.



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    Re: Error :Syntax error near "module"

    Please post the error msg you get.
    FPGA enthusiast!



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    Re: Error :Syntax error near "module"

    Quote Originally Posted by abimann View Post
    I just try to compile, and it gave me ERROR.
    Maybe you told Vivado that it's a VHDL file?


    1 members found this post helpful.

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  6. #6
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    Re: Error :Syntax error near "module"

    Quote Originally Posted by std_match View Post
    Maybe you told Vivado that it's a VHDL file?
    Excellent catch... here is what Modelsim shows when compiling in verilog and vhdl
    Code:
    C:\test\edaboard>vlog neso_ddr3.v
    Start time: 07:42:41 on Mar 26,2020
    vlog neso_ddr3.v
    Model Technology ModelSim DE-64 vlog 10.5b Compiler 2016.05 May 21 2016
    -- Compiling module neso_ddr3
    
    Top level modules:
            neso_ddr3
    End time: 07:42:41 on Mar 26,2020, Elapsed time: 0:00:00
    Errors: 0, Warnings: 0
    Code:
    C:\tes\edaboard>vcom neso_ddr3.v
    Start time: 07:42:56 on Mar 26,2020
    vcom neso_ddr3.v
    Model Technology ModelSim DE-64 vcom 10.5b Compiler 2016.05 May 21 2016
    -- Loading package STANDARD
    ** Error: neso_ddr3.v(1): near "module": syntax error
    End time: 07:42:56 on Mar 26,2020, Elapsed time: 0:00:00
    Errors: 1, Warnings: 0



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    Re: Error :Syntax error near "module"

    Possibly...
    But the OP is using vivado 19. which makes default use of xsim compiler.
    The OP was not specific about the compiler used.
    FPGA enthusiast!



  8. #8
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    Re: Error :Syntax error near &quot;module&quot;

    i create VHDL file and paste verilog code. thanks

    - - - Updated - - -

    I think , i make it working.

    but here is other problem,

    The VHDL concatenate operator is ampersand (&) and what is analogue in Verilog ? or how to do ?

    How to add incoming switch signal to reg like in VHDL for example reg <= "01" & "010101" , reg equal reg <= "01010101" ?

    output [29:0] led,
    input [3:0] sw
    );
    .................

    reg [127:0] data_to_write = {32'h00AAAAAA, 32'hAAAAAAAA, 32'hAAAAAAAA, 31'hAAAAAAF, 1'b0000};
    reg [127:0] data_to_write = {32'h00AAAAAA, 32'hAAAAAAAA, 32'hAAAAAAAA, 31'hAAAAAAF} & {sw}; ?
    Last edited by abimann; 27th March 2020 at 16:05.



  9. #9
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    Re: Error :Syntax error near &quot;module&quot;

    You should read a verilog book are at least an online tutorial

    Code:
    reg [127:0] data_to_write = {32'h00AAAAAA, 32'hAAAAAAAA, 32'hAAAAAAAA, 31'hAAAAAAF, sw};
    to concatenate stuff in Verilog just use {} and stick everything inside separated by the , character.

    FYI if you use an integer in a concatenation it is always dependent on the interpretation of integer on your system and in the simulator/synthesis tool so it is usually 32-bits but might be 64-bits on some implementations, i.e. don't use integers in a concatenate.

    - - - Updated - - -

    Quote Originally Posted by dpaul View Post
    Possibly...
    But the OP is using vivado 19. which makes default use of xsim compiler.
    The OP was not specific about the compiler used.
    Doesn't mater that the OP is using Vivado. Vivado Simulation compiler has the following two commands (scripts) xvlog and xvhdl to compile the different languages.

    I believe these are scripts that call the same base compiler but with different switches. So if you tell the tools a Verilog file is VHDL it will compile it as if it's a VHDL file resulting in the error on the module declaration.



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    Re: Error :Syntax error near "module"

    it says:

    [Synth 8-1002] sw is not a constant ["C:/Users/umt/Documents/cam_ddr_pipe/cam_ddr_pipe.srcs/sources_1/new/veri.v":64]
    what is that mean, it need to assign to some register ? I plan to put data from camera , of cause that 's no constant.
    Last edited by abimann; 27th March 2020 at 17:30.



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    Re: Error :Syntax error near "module"

    You shouldn't be assigning anything to a reg in it's declaration, this may or may not work in an FPGA some tools will use that as the power up state of the register.

    If you need to set a register state at the beginning you should use a flip-flop with a reset and the reset value can use another signal.

    If you need to register you data from the camera then it should be in a edge triggered always block.

    Why are you insisting on writing code before knowing the basic syntax of Verilog? Learn the syntax then write code.



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    Re: Error :Syntax error near "module"

    Yes, now i have a lot of time, due to the covid19. Will learn Verilog as I will print it out.
    one questioin is in shortest time need to be find.:

    WRITE_DONE: begin
    if (app_rdy & app_en) begin
    app_en <= 0;
    end

    if (app_wdf_rdy & app_wdf_wren) begin
    app_wdf_wren <= 0;
    end

    if (~app_en & ~app_wdf_wren) begin
    state <= READ;
    end
    end
    is equal to VHDL folowing code :

    WHEN WRITE_DONE =>
    if (app_rdy = '1') and (app_en ='1') then
    app_en <= '0';
    end if;

    if (app_wdf_rdy = '1') and (app_wdf_wren = '1') then
    app_wdf_wren <= '0';
    end if;

    if (not app_en = '1') and (not app_wdf_wren = '1') then
    state <= READ;
    end if;



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  13. #13
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    Re: Error :Syntax error near &quot;module&quot;

    Yes, now i have a lot of time, due to the covid19. Will learn Verilog as I will print it out.
    one questioin is in shortest time need to be find.:

    WRITE_DONE: begin
    if (app_rdy & app_en) begin
    app_en <= 0;
    end

    if (app_wdf_rdy & app_wdf_wren) begin
    app_wdf_wren <= 0;
    end

    if (~app_en & ~app_wdf_wren) begin
    state <= READ;
    end
    end
    is equal to VHDL folowing code ??? :

    WHEN WRITE_DONE =>
    if (app_rdy = '1') and (app_en ='1') then
    app_en <= '0';
    end if;

    if (app_wdf_rdy = '1') and (app_wdf_wren = '1') then
    app_wdf_wren <= '0';
    end if;

    if (not app_en = '1') and (not app_wdf_wren = '1') then
    state <= READ;
    end if;
    - - - Updated - - -

    equal or not?



  14. #14
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    Re: Error :Syntax error near "module"

    they are equivalent, but I would suggest never writing stuff like this:
    Code VHDL - [expand]
    1
    2
    3
    
    if (not app_en = '1') and (not app_wdf_wren = '1') then
    state <= READ;
    end if;
    It doesn't follow a KISS rule.

    It should be written in a direct form that doesn't required comparing inverted signals
    Code VHDL - [expand]
    1
    2
    3
    
    if (app_en = '0') and (app_wdf_wren = '0') then
    state <= READ;
    end if;
    That syntax clearly states what comparison is being done.


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