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  1. #1
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    Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Greetings ... comment that I am with a small project in ISE 14.5, I have managed to synthesize but I am having compatibility problems with the ipcore fifo_generator 9.3 when implementing and I am having one of the errors.

    Code:
    ERROR:NgdBuild:604 - logical block 'u_client[0].U_client_ff' with type
       'g1_ipcat_wbus_client_fifo' could not be resolved. A pin name misspelling can
       cause this, a missing edif or ngc file, case mismatch between the block name
       and the edif or ngc file name, or the misspelling of a type name. Symbol
       'g1_ipcat_wbus_client_fifo' is not supported in target 'virtex5'.
    The project is for a Virtex5 device (xc5vlx155t-3ff1136) and the code I am using is the following:

    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    USE ieee.std_logic_misc.all;
    
    entity g1_wbus_client_fifos_vhdl is
      Port ( 
        -- Clock and reset
        i_aur_clk      : IN std_logic;	                    -- Aurora fabric clock
        i_rst          : IN std_logic;                      -- General async reset   
    
        -- wbus stack interface
        o_wbus_ready   : OUT std_logic;    
        i_wbus_wen     : IN std_logic;                      -- wbus write enable   
        i_wbus_addr    : IN std_logic_vector(31 DOWNTO 0);  -- wbus write address    
        i_wbus_data    : IN std_logic_vector(31 DOWNTO 0);  -- wbus write data 
    
        -- 26 Client Channels
        i_wbus_enable  : IN std_logic_vector(25 DOWNTO 0);  -- Allow writes to wbus fifo    
        i_wbus_fws     : IN std_logic_vector(129 DOWNTO 0); -- 5-bit FIFO window select for each channel    
        i_wbus_clk     : IN std_logic_vector(25 DOWNTO 0);  -- Client clock    
        o_wbus_empty   : OUT std_logic_vector(25 DOWNTO 0); -- fifo empty   
        i_wbus_ren     : IN std_logic_vector(25 DOWNTO 0);  -- Fifo read enable    
        o_wbus_count   : OUT std_logic_vector(259 DOWNTO 0);-- Available data words 10 bits    
        --o_wbus_valid   : OUT std_logic_vector(25 DOWNTO 0); -- Address and Data valid    
        o_wbus_wdata   : OUT std_logic_vector(831 DOWNTO 0);-- Write Data 32 bits each    
        o_wbus_waddr   : OUT std_logic_vector(831 DOWNTO 0);-- Write Address 19 bits valid    
    			 
        -- Status and Test Points
        o_ro_wbus_debug : OUT std_logic_vector(31 DOWNTO 0);-- Output status bits for a debug register    
        o_test_points  : OUT std_logic_vector(3 DOWNTO 0)   -- test points
      );
    end g1_wbus_client_fifos_vhdl;
    
    architecture Behavioral of g1_wbus_client_fifos_vhdl is
    
    Component g1_ipcat_wbus_client_fifo
      port(
        rst           : in std_logic;               
        wr_clk        : in std_logic;           
        din           : in std_logic_vector(51 downto 0);               
        wr_en         : in std_logic;                 
        full          : out std_logic;                    
        wr_data_count : out std_logic_vector(9 downto 0);      
           
        -- The Client Port is connected to all the read signals
                                              
        rd_clk        : in std_logic;     
        rd_en         : in std_logic;     
        dout          : out std_logic_vector(51 downto 0);             
        empty         : out std_logic;   
        rd_data_count : out std_logic_vector(9 downto 0)     
        --valid         : out std_logic        
      );
    end component;  
    
    CONSTANT Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100";  
    type  wbus_count_type is array(0 to 25) of std_logic_vector(9 downto 0);
    type  array_26x10 is array(0 to 25) of std_logic_vector(9 downto 0);
    type  array_26x52 is array(0 to 25) of std_logic_vector(51 downto 0);
    SIGNAL almost_full      : std_logic_vector(25 DOWNTO 0);
    SIGNAL ffdin            : std_logic_vector(51 DOWNTO 0);
    SIGNAL ff_dout          : array_26x52;
    SIGNAL ff_write_count   : array_26x10;	
    SIGNAL wbus_count       : wbus_count_type;	
    SIGNAL wbr_d            : std_logic;
    SIGNAL upper_adrs_match : std_logic;
    SIGNAL wen              : std_logic_vector(25 downto 0);
    SIGNAL almost_full_d    : std_logic_vector(25 downto 0);
    SIGNAL wbus_addr_fws    : std_logic_vector(25 downto 0);
    begin
    
    -- A fifo is implemented for each client port.
    
    ffdin <= i_wbus_addr(19 downto 0) & i_wbus_data(31 downto 0);
    
    -- Note: Software must monitor the level of each FIFO is some way in order to prevent
    -- Almost_Full_Depth from being reached. 
           
    u_client : for idx in 0 to 25 generate
      begin       
        o_wbus_count(10*idx+9 downto 10*idx)    <= wbus_count(idx); -- Convert from 2D to 1D vector.       
        
        -- Uppermost 2 bits of 8MB Auter space must be 0's
        upper_adrs_match                        <= '1';       
    		
        -- Write only one fifo by decoding 5 address bits.
        wbus_addr_fws(idx)  <= '1' when (i_wbus_addr(20 downto 16) = i_wbus_fws(5*idx+4 downto 5*idx)) else '0';          
        wen(idx)            <= i_wbus_enable(idx) and i_wbus_wen and upper_adrs_match and wbus_addr_fws(idx);
    		
        almost_full_d(idx)  <= i_wbus_enable(idx) and '1' when (ff_write_count(idx) > Almost_Full_Depth) else '0';
        
        -- partslib_pkg.vhd: Simple DFF with Clock enable e.    
        dc_amf: entity work.dreg_clr_vhdl generic map(1)
          port map( 
            c   => i_aur_clk, 
            ar  => i_rst, 
            e   =>  '1', 
            d(0)   => almost_full_d(idx), 
            q(0)   => almost_full(idx)  
          );
    			
        -- 52 bits x 512, First Word Fall Through.
        U_client_ff: g1_ipcat_wbus_client_fifo  
          port map(
            rst           => i_rst,              -- input rst             
            wr_clk        => i_aur_clk,          -- input wr_clk       
            din           => ffdin,              -- input [51 : 0] din        
            wr_en         => wen(idx),           -- input wr_en              
            full          => open,               -- output full                  
            wr_data_count => ff_write_count(idx),-- output [9 : 0] wr_data_count      
           
            -- The Client Port is connected to all the read signals
                                              
            rd_clk        => i_wbus_clk(idx),    -- input rd_clk    
            rd_en         => i_wbus_ren(idx),    -- input rd_en    
            dout          => ff_dout(idx),       -- output [51 : 0] dout            
            empty         => o_wbus_empty(idx),  -- output empty  
            rd_data_count => wbus_count(idx)    -- output [9 : 0] rd_data_count     
            --valid         => o_wbus_valid(idx)   -- output valid   
          ); 
        
        -- o_wbus_waddr is divided into 32 bit widths for convenience
        -- even though only the lowest 19 bits are used.
                         
        o_wbus_waddr(32*idx+31 downto 32*idx)   <= "0000000000000" & ff_dout(idx)(50 downto 32);
        o_wbus_wdata(32*idx+31 downto 32*idx)   <= ff_dout(idx)(31 downto 0);
                
    end generate u_client;
        
    wbr_d <= NOT OR_REDUCE (almost_full);
    
    -- partslib_pkg.vhd: Simple DFF with Clock enable e.    
    dc_wbr : entity work.dreg_clr_vhdl generic map(1)
      PORT MAP (
        c    => i_aur_clk,
        ar   => i_rst,
        e    => '1',
        d(0) => wbr_d,
        q(0) => o_wbus_ready);
    
    -- This output port is for a diagnostic register to read back the 'almost_full' flag of each client fifo.           
    o_ro_wbus_debug <= X"E" & "00" & almost_full(25 DOWNTO 0); --The '0xE' in the msb nibble is just for
                                                               -- identifying purposes.
    
    o_test_points <= x"0";              
    end Behavioral;
    I leave attached the ipcore fifo_generator, any help is welcome. Thanks in advance.

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  2. #2
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    Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    That errors looks like the kind you get when you don't include the core in your design.

    As this is ISE I was expecting to see an XCI file in the directory, but there isn't one, that is normally what I always added to my ISE project for an IP core from coregen.



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  3. #3
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    Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    thanks for the help ads-ee ... tell you that ISE coregen creates the XCO file, which I could add to my project and solve that error with ipcore, but now I am having a similar error in another module when using the unisim library.

    Code:
    ERROR:NgdBuild:604 - logical block
       'U_pim1_vhdl/U_g1_applic_top_vhdl/U_g1_hotlink_pim_vhdl/HL_TXCLK[1].u_iodelay
       _txclk' with type 'ODELAYE2' could not be resolved. A pin name misspelling
       can cause this, a missing edif or ngc file, case mismatch between the block
       name and the edif or ngc file name, or the misspelling of a type name. Symbol
       'ODELAYE2' is not supported in target 'virtex5'.



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  4. #4
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    Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Unisim is not used to implement a design, so I'm not sure why you think unisim is causing the NgdBuild error.

    From the Virtex5 library guide ODELAYE2 is not a Virtex 5 primitive, it turns out it is a primitive from Virtex7. I'm not sure how you are doing your design but you seem to be mixing different families.



  5. #5
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    Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    the truth is that the project was done in Vivado 2017.3 for a virtex-7 and I am trying to adapt it for a virtex-5, but I am a novice in ISE. I just saw the Virtex-5 FPGA User Guide datasheet (p. 370) https://www.xilinx.com/support/docum...ides/ug190.pdf and was able to verify that there is an equivalent primitives for ODELAYE2 and OSERDESE2 (OSERDES and IODELAY) for Virtex-5, but the problem is that OSERDES only has 6 inputs parallel data and I require 8. Any suggestions with this problem?



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  6. #6
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    Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Quote Originally Posted by Cesar0182 View Post
    equivalent primitives for ODELAYE2 and OSERDESE2 (OSERDES and IODELAY) for Virtex-5, but the problem is that OSERDES only has 6 inputs parallel data and I require 8. Any suggestions with this problem?
    Not equivalent, just a similar type of function You will have to redesign, both the SERDES block implementation and the interface to the FPGA logic.

    Generally if you need to port to a new family you have to generate new cores that fit the architecture of the family. If it's something like instantiated IO primitives (i.e. like the OSERDES), then you need to determine how the interface signaling was done on the original design and create a new design that handles the same signalling. The internal FPGA logic interface will be different between families, so you will have to redesign that logic to support the family you are porting to.



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