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  1. #1
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    128 x 32 single port RAM VHDL code problem

    I have a code and testbench for 128 x 32 single port RAM VHDL code, but the wave that I get is not correct. I am using a protected testbench created by my instructor. How should I change the code, I am on the learning process about RAM/ROM memories, so if you know something that I have to put in my code, please comment. Thanks

    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.ALL;
    
    ENTITY RAM128_32 IS
    	PORT
    	(
    		address	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    		clock		: IN STD_LOGIC  := '1';
    		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    		wren		: IN STD_LOGIC ;
    		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    	);
    END RAM128_32;
    
    architecture syn_ram of RAM128_32 is 
    
    	type ram_type is array (127 downto 0) of std_logic_vector(31 downto 0);
    	signal RAM : ram_type;
    	signal read_a : std_logic_vector(6 downto 0);
    	
    	begin
    		process(clock)
    		begin
    			if rising_edge(clock) then   
    				if (wren = '1') then   
    				RAM(to_integer(unsigned(address))) <= data;   
    				end if;   
    			read_a <= address;   
    			end if;   
    		end process;   
    	q <= RAM(to_integer(unsigned(read_a)));   
    	end syn_ram;
    And this is the protected testbench:
    Code:
    --------------------------------------------------------------------------------
    --                                                                            --
    --                            RAM Test Bench                                  --
    --                                                                            --
    ----------------------------------------------
    
    library ieee;                                
    use ieee.std_logic_1164.all;                 
    use ieee.numeric_std.all; 
    use ieee.numeric_bit_unsigned.all;
    use ieee.std_logic_textio.all;
    use std.textio.all;
    use work.all;
    
    ----------------------------------------------------------------------
    -- Testbench entity declaration
    ----------------------------------------------------------------------
    entity AAC2M2P2_tb is 
    --  port( ); 
    -- no external interface.....THIS IS THE TOP LEVEL
    end AAC2M2P2_tb;
    
    -------------------------------------------------------------------
    -- Testbench architecture body
    ----------------------------------------------------------------------
    architecture behavioral of AAC2M2P2_tb is      
    ----------------------------------------------------------------------
    --- constant declarations
    ----------------------------------------------------------------------
       constant delay:  TIME := 10 NS; -- defines the wait period.
       constant Points: integer := 10;   -- number of points this problem
                                        -- is worth
    
    ----------------------------------------------------------------------                                                                      
    -- signal declarations 
    ----------------------------------------------------------------------
      signal clock_tb:  std_logic := '0'; --clock in
      signal address_tb:  std_logic_vector(6 downto 0);  -- address input
      signal data_tb:  std_logic_vector(31 downto 0);  -- data input
      signal wren_tb:  std_logic := '0'; -- write enable input
      signal q_tb:  std_logic_vector(31 downto 0);  -- output
    
      signal simend :std_logic :='0'; -- signal to end simulation, used to stop clock process
    
      signal ValidCheck: std_logic_vector(15 downto 0);  
                -- unique to this problem, to check validity of submission
      type mem is array (integer range <>) of std_logic_vector(7 downto 0);
      signal ROM: mem(0 to 255);
    
    --------------------------------------------------
    -- component declarations before instantiation 
    --------------------------------------------------
    ---------------------------------------------------------------------
    -- Component declarations
    ----------------------------------------------------------------------
    Component RAM128_32  -- 
       port(
    		address		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    		clock		: IN STD_LOGIC  := '1';
    		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    		wren		: IN STD_LOGIC ;
    		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
       );
    end component RAM128_32;
    
    ----------------------------------------------------------------------
    --- Procedures
    ----------------------------------------------------------------------
    
      procedure Load_ROM(signal data_word : inout mem) is
         file ROMfile : text open read_mode is "vectorh.out";
         variable lbuf: line;
         variable i: integer :=0;
         variable fdata: std_logic_vector(7 downto 0);
     --
       begin
         while not(endfile(ROMfile))  loop
         -- read digital data from input file
         readline(ROMfile, lbuf);
         hread(lbuf, fdata);
         data_word(i) <= fdata;
         i := i + 1;
         end loop;
      end procedure; 
    
     procedure Write_ROM (signal data_word : inout mem) is
         file ROMfileOut : text open write_mode is "myvectorh.out";
         variable row: line;
         variable i : integer :=0;
         variable fdata: std_logic_vector (7 downto 0);
     --
       begin
         while (i<256) loop
         fdata := data_word(i);
         hwrite(row, fdata, left,4);
         writeline(RomfileOut, row);
         i := i + 1;
         end loop;
      end procedure;
    
    ----------------------------------------------------------------------
    -- Top level output port assignments
    ----------------------------------------------------------------------
    begin
     ----------------------------------------------------------------------
    -- Component instances
    ----------------------------------------------------------------------
    -- RAM128_32
    RAM_Test : RAM128_32 PORT MAP (
    		address	 => address_tb,
    		clock	 => clock_tb,
    		data	 => data_tb,
    		wren	 => wren_tb,
    		q	 => q_tb
    	);
    
    `protect BEGIN_PROTECTED
    `protect version = 1
    `protect encrypt_agent = "ModelSim", encrypt_agent_info = "10.4a"
    `protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-1" , key_method = "rsa"
    `protect encoding = (enctype = "base64", line_length = 64, bytes = 128)
    `protect KEY_BLOCK
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    `protect data_method = "aes128-cbc"
    `protect encoding = (enctype = "base64", line_length = 64, bytes = 4196)
    
    `protect DATA_BLOCK
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    `protect END_PROTECTED
    end behavioral;
    here's the waveform:
    Click image for larger version. 

Name:	RAM.PNG 
Views:	11 
Size:	295.8 KB 
ID:	158387
    Last edited by chandlerbing65nm; 24th March 2020 at 20:11.

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  2. #2
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    Re: 128 x 32 single port RAM VHDL code problem

    no idea. can you at least describe what you are expecting versus what you are getting?

    ps: tell your instructor memories are not synthesisable, this is a very poor exercise.
    Really, I am not Sam.



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  3. #3
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    Re: 128 x 32 single port RAM VHDL code problem

    ps: tell your instructor memories are not synthesisable, this is a very poor exercise.
    The code looks like a template to infer FPGA block RAM. In so far it's well synthesizable.



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  4. #4
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    Re: 128 x 32 single port RAM VHDL code problem

    Quote Originally Posted by ThisIsNotSam View Post
    no idea. can you at least describe what you are expecting versus what you are getting?

    ps: tell your instructor memories are not synthesisable, this is a very poor exercise.
    Im not quite sure what you're talking about, Ive been infering rams using templates like this for 15+ years (since I started at UNI).



  5. #5
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    Re: 128 x 32 single port RAM VHDL code problem

    ThisIsNotSam is thinking ASIC designs not FPGA....FPGAs you can infer RAM. ASICs well that's why there are memory compilers.



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    Re: 128 x 32 single port RAM VHDL code problem

    Quote Originally Posted by ads-ee View Post
    ThisIsNotSam is thinking ASIC designs not FPGA....FPGAs you can infer RAM. ASICs well that's why there are memory compilers.
    correct. disregard my message... wrong forum.
    Really, I am not Sam.



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  7. #7
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    Re: 128 x 32 single port RAM VHDL code problem

    The other point in post #2 is nevertheless true. We don't see which part of the wave is incorrect, we don't even know which part of the code has been created by you and what's the exercise specification.

    To run the simulation, we would need the ROM image file vectorh.out.



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