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A Code issue in Verilog

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tahirsengine

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Hi,
Please see the code below:

Code:
module ha ( input   a, b,
            output  sum, cout);
 
  assign sum  = a ^ b;
  assign cout = a & b;
endmodule


Code:
module my_design 
  #(parameter N=4) 
    (  input [N-1:0] a, b,
      output [N-1:0] sum, cout);
 

  generate 
    for (i = 0; i < N; i = i + 1) begin
          ha u0 (a[i], b[i], sum[i], cout[i]);
    end
  endgenerate
endmodule

As in above example, we saw that ha was generated N times. The issue that I can not understand is, all the generated instances will get an instance name as u0. But this code actually works. But doesn't the instance names should be unique? How come this is working, and that works actually!
 

the generate gives each instance a unique path
 

The compiler assigns unique hierarchical names for unnamed generates, review LRM 27.6.
 

Thanks for replies.
Actually the source of my confusion is as follows.

Here is a generate code:

Code:
generate
    genvar row;
    for (row=0;row<5;row=row+1) begin : I_ROW
     AND CU (.a(row),.b(row),.c(row));
      genvar j;
      for (j=0;j<8;j=j+1) begin : CELL
        OR LA (.a(j),.b(j),.c(j)), 
      end   
    end
  endgenerate

As it might be seen that there are two for loops. I wanted to force c outputs in OR LA loop. I also checked the following thread:
https://www.edaboard.com/showthread...rce-a-generate-block-signal-in-System-Verilog

but confusion is, how to deal with this double for loop.

@FvM @TrickyDicky @dave_59
 

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