+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Member level 2
    Points: 683, Level: 5

    Join Date
    Apr 2018
    Posts
    50
    Helped
    0 / 0
    Points
    683
    Level
    5

    Delay time calculation

    Hi guys,

    I'm just curious and not able to found the answer in the internet, how to calculate the delay using clock cycles.
    I have read that the equation is :

    Clock cycles =(time delay) *(clock frequency/4).

    how did it come to that equation (divide by 4). Thanks

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 2
    Points: 3,150, Level: 13

    Join Date
    Jan 2019
    Posts
    574
    Helped
    150 / 150
    Points
    3,150
    Level
    13

    Re: Delay time calculation

    which processor, FPGA, or other digital IC are you using?
    the answer is likely in the data sheet, buried in how the device handles the clock


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  3. #3
    Member level 2
    Points: 683, Level: 5

    Join Date
    Apr 2018
    Posts
    50
    Helped
    0 / 0
    Points
    683
    Level
    5

    Re: Delay time calculation

    I'm using Altera DE10-Lite FPGA Development board. I can't find the specs where I'm supposed to know the relationship between clock frequency, cycles and delay. It have 2 50MHz clocks that I'm using.

    Here are the product files:
    m10_handbook.pdf
    m10_datasheet.pdf
    DE10-Lite_User_Manual.pdf



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 2
    Points: 3,150, Level: 13

    Join Date
    Jan 2019
    Posts
    574
    Helped
    150 / 150
    Points
    3,150
    Level
    13

    Re: Delay time calculation

    i looked in all three docs you posted and did not find what you're asking about.
    where did you find

    Clock cycles =(time delay) *(clock frequency/4).


    see "Fine Resolution Phase Shift" page 166 of handbook
    see "PLL outputs" page 155
    see "Figure 6-1: PLL Output Clock Frequency" page 212



  5. #5
    Super Moderator
    Points: 32,397, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,489
    Helped
    1758 / 1758
    Points
    32,397
    Level
    43

    Re: Delay time calculation

    Quote Originally Posted by chandlerbing65nm View Post
    I'm using Altera DE10-Lite FPGA Development board. I can't find the specs where I'm supposed to know the relationship between clock frequency, cycles and delay. It have 2 50MHz clocks that I'm using.

    Here are the product files:
    m10_handbook.pdf
    m10_datasheet.pdf
    DE10-Lite_User_Manual.pdf
    I don't get what your issue is exactly (which is why I ignored your first post).

    A clock has a frequency, in your case it is 50 MHz. That clock therefore has a clock period of 20 ns between each rising edge, i.e. 1/(50 MHz) = 20e-9. Therefore 1 clock cycle is 20 ns of delay.

    If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.


    I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.



  6. #6
    Advanced Member level 5
    Points: 41,023, Level: 49

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,607
    Helped
    1949 / 1949
    Points
    41,023
    Level
    49

    Re: Delay time calculation

    Perhaps there is a built-in clock prescaler (like, to make
    a 4-phase field from a 50MHz main clock)?



    •   AltAdvertisement

        
       

  7. #7
    Super Moderator
    Points: 81,979, Level: 69
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    16,637
    Helped
    3771 / 3771
    Points
    81,979
    Level
    69

    Re: Delay time calculation

    Hi,

    If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.

    I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.
    In my eyes there is no clock divider .... indeed I expect a clock multiplier. (PLL)
    Clock cycles =(time delay) *(clock frequency/4).
    If you replace with the values of your post:
    Clock cycles = 25
    Time delay = 500ns
    Clock frequency = 12.5MHz
    Then the formula is not correct
    But if you replace with: clock frequency = 200MHz
    Then the formula is correct.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



  8. #8
    Super Moderator
    Points: 32,397, Level: 43
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,489
    Helped
    1758 / 1758
    Points
    32,397
    Level
    43

    Re: Delay time calculation

    Quote Originally Posted by KlausST View Post
    Hi,


    In my eyes there is no clock divider .... indeed I expect a clock multiplier. (PLL)
    Clock cycles =(time delay) *(clock frequency/4).
    If you replace with the values of your post:
    Clock cycles = 25
    Time delay = 500ns
    Clock frequency = 12.5MHz
    Then the formula is not correct
    But if you replace with: clock frequency = 200MHz
    Then the formula is correct.

    Klaus
    My oops, good catch.



--[[ ]]--