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23rd March 2020, 23:17 #1
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Delay time calculation
Hi guys,
I'm just curious and not able to found the answer in the internet, how to calculate the delay using clock cycles.
I have read that the equation is :
Clock cycles =(time delay) *(clock frequency/4).
how did it come to that equation (divide by 4). Thanks

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24th March 2020, 01:35 #2
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Re: Delay time calculation
which processor, FPGA, or other digital IC are you using?
the answer is likely in the data sheet, buried in how the device handles the clock
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25th March 2020, 16:55 #3
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Re: Delay time calculation
I'm using Altera DE10Lite FPGA Development board. I can't find the specs where I'm supposed to know the relationship between clock frequency, cycles and delay. It have 2 50MHz clocks that I'm using.
Here are the product files:
m10_handbook.pdf
m10_datasheet.pdf
DE10Lite_User_Manual.pdf

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25th March 2020, 17:33 #4
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Re: Delay time calculation
i looked in all three docs you posted and did not find what you're asking about.
where did you find
Clock cycles =(time delay) *(clock frequency/4).
see "Fine Resolution Phase Shift" page 166 of handbook
see "PLL outputs" page 155
see "Figure 61: PLL Output Clock Frequency" page 212

25th March 2020, 17:43 #5
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Re: Delay time calculation
I don't get what your issue is exactly (which is why I ignored your first post).
A clock has a frequency, in your case it is 50 MHz. That clock therefore has a clock period of 20 ns between each rising edge, i.e. 1/(50 MHz) = 20e9. Therefore 1 clock cycle is 20 ns of delay.
If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.
I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.

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26th March 2020, 01:29 #6
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Re: Delay time calculation
Perhaps there is a builtin clock prescaler (like, to make
a 4phase field from a 50MHz main clock)?

26th March 2020, 02:14 #7
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Re: Delay time calculation
Hi,
If you want to have 500 ns of delay then you have 500 ns/20 ns = 25 clock cycles of the 50 MHz clock will create that much delay.
I have no idea where that equation you showed "Clock cycles =(time delay) *(clock frequency/4)." came from but it requires the clock to be 1/4 of the 50 MHz, i.e. 12.5 MHz.
Clock cycles =(time delay) *(clock frequency/4).
If you replace with the values of your post:
Clock cycles = 25
Time delay = 500ns
Clock frequency = 12.5MHz
Then the formula is not correct
But if you replace with: clock frequency = 200MHz
Then the formula is correct.
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

26th March 2020, 15:35 #8
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